TDA7319 查看數據表（PDF） - STMicroelectronics
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TDA7319 Datasheet PDF : 16 Pages
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TDA7319
SDA, SCL I2CBUS TIMING
Symbol
fSCL
tBUF
tHD:STA
tLOW
tHIGH
tSU:STA
tHD:DA
tSU:DAT
tR
tF
tSU:STO
Parameter
SCL clock frequency
Bus free time between a STOP and START condition
Hold time (repeated) START condition. After this period, the first
clock pulse is generated
LOW period of the SCL clock
HIGH period of the SCL clock
Set-up time for a repeated START condition
Data hold time
Data set-up time
Rise time of both SDA and SCL signals
Fall time of both SDA and SCL signals
Set-up time for STOP condition
All values referred to VIH min. and VIL max. levels
(*) Must be guaranteed by the I2C BUS master.
Min.
0
1.3
0.6
1.3
0.6
0.6
0.300
100
20
20
0.6
Typ.
Max.
400
300
300
Unit
kHz
µs
µs
µs
µs
µs
µs
ns
ns (*)
ns (*)
µs
Definition of timing on the I2C-bus
SDA
tBUF
tR tF
SCL
tLOW
P
S tHD;STA
P = STOP
S = START
tHD;DAT
tHIGH
tF
tHD;STA
tSP tSU;STO
tSU;STA
tSU;DAT
Sr
P
D95AU314
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