TDA7468D 查看數據表（PDF） - STMicroelectronics

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TDA7468D

TWO BANDS DIGITALLY CONTROLLED AUDIO PROCESSOR WITH BASS ALC SURROUND

STMicroelectronics 

TDA7468D

5 SOFTWARE SPECIFICATION

Interface Protocol

The interface protocol comprises:

■ A start condition (S)

■ A chip address byte, containing the TDA7468D address

■ A subaddress bytes

■ A sequence of data (N byte + acknowledge)

■ A stop condition (P)

CHIP ADDRESS

SUBADDRESS

DATA 1 to DATA n

MSB

LSB

MSB

S 1 0 0 0 1 0 0 0 ACK X X X B

D96AU420

ACK = Acknowledge

S = Start; P = Stop

A = Address

B = Auto Increment

LSB

MSB

DATA

ACK

DATA

LSB

ACK P

6 EXAMPLES

6.1 No Incremental Bus

The TDA7468D receives a start condition, the correct chip address, a subaddress with the B = 0 (no in-

cremental bus), N-data (all these data concern the subaddress selected), a stop condition.

CHIP ADDRESS

SUBADDRESS

MSB

LSB

MSB

LSB

MSB

S 1 0 0 0 1 0 0 0 ACK X X X 0 D3 D2 D1 D0 ACK

D96AU421

DATA

DATA

LSB

ACK P

6.2 Incremental Bus

The TDA7468D receive a start conditions, the correct chip address, a subaddress with the B = 1 (incre-

mental bus): now it is in a loop condition with an autoincrease of the subaddress whereas SUBADDRESS

from "XXX1000" to "XXX1111" of DATA are ignored.

The DATA 1 concern the subaddress sent, and the DATA 2 concern the subaddress sent plus one in the

loop etc, and at the end it receivers the stop condition.

CHIP ADDRESS

SUBADDRESS

DATA 1 to DATA n

MSB

LSB

MSB

LSB

MSB

S 1 0 0 0 1 0 0 0 ACK X X X 1 D3 D2 D1 D0 ACK

D96AU422

DATA

LSB

ACK P

Table 5. POWER ON RESET CONDITION

MSB

LSB

D7

D6

D5

D4

D3

D2

D1

D0

1

1

1

1

1

1

1

0

9/22

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