TDA8044 查看數據表（PDF） - Philips Electronics

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TDA8044

Satellite demodulator and decoder

Philips Electronics 

Philips Semiconductors

Satellite demodulator and decoder

Product specification

TDA8044

FEATURES

• General features:

– One-chip Digital Video Broadcasting (DVB)

compliant Quadrature Phase Shift Keying (QPSK)

and Binary Phase Shift Keying (BPSK) demodulator

and concatenated Viterbi/Reed-Solomon decoder

with de-interleaver and de-randomizer

(ETS 300 421)

– 3.3 V supply voltage (input pads are 5 V tolerant)

– Standby mode for low power dissipation

– Internal clock PLL to allow low frequency crystal

application and selectable clock frequencies

– Power-on reset module

– Package: QFP100

– Boundary scan test.

• QPSK/BPSK demodulator:

– Interpolator and anti-alias filter to handle a large

range of symbol rates without additional external

filtering

– On-chip AGC of the analog input I and Q baseband

signals or tuner AGC control

– Two on-chip matched Analog-to-Digital Converters

(ADCs; 7 bits)

– Half Nyquist (square root raised-cosine) filter with

selectable roll-off factor

– Large range of symbol frequencies:

0.5 to 45 Msymbols/s for TDA8044 and

0.5 to 30 Msymbols/s for TDA8044A, including

Single Carrier Per Channel (SCPC) function

– Can be used at low channel Signal-to-Noise ratio

(S/N)

– Internal carrier recovery, clock recovery and AGC

loops with programmable loop filters

– Two loop carrier recovery enabling phase tracking of

the incoming symbols

– Software carrier sweep for low symbol rate

applications

– Signal-to-noise ratio estimation

– External indication of demodulator lock.

• Viterbi decoder:

– Rate 1⁄2 convolutional code based

– Constraint length K = 7 with G1 = 171oct and

G2 = 133oct; supported puncturing code rates:

1⁄2, 2⁄3, 3⁄4, 4⁄5, 5⁄6, 6⁄7, 7⁄8 and 8⁄9

– 4 bits input for ‘soft decision’ for both I and Q

– Truncation length: 144

– Automatic synchronization

– Channel Bit Error Rate (BER) estimation

– External indication of Viterbi sync lock

– Differential decoding optional.

• Reed-Solomon (RS) decoder:

– (204, 188, T = 8) Reed-Solomon code

– Automatic (I2C-bus configurable) synchronization of

bytes, transport packets and frames

– Internal convolutional de-interleaving (I = 12; using

internal memory)

– De-randomizer based on Pseudo Random Bit

Sequence (PRBS)

– External indication of Register Select (RS) decoder

sync lock

– External indication of uncorrectable error (transport

error indicator is set)

– External indication of corrected byte

– Indication of the number of lost blocks

– Indication of the number of corrected blocks.

• Interface:

– I2C-bus interface to initialize and monitor the

demodulator and Forward Error Correction (FEC)

decoder; when no I2C-bus usage, default mode is

defined

– Programmable interrupt facility

– 6 bits I/O expander for flexible access to and from the

I2C-bus

– Switchable I2C-bus loop-through to suppress I2C-bus

crosstalk in the tuner

– DiSEqC level 1.X support for dish control applications

– 3-state mode for transport stream outputs.

APPLICATIONS

• Digital satellite TV: demodulation and Forward Error

Correction (FEC).

2000 Feb 21

2

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