TDA8764HL 查看數據表（PDF） - Philips Electronics

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TDA8764HL

10-bit high-speed low-power ADC with internal reference regulat

Philips Electronics 

Philips Semiconductors

10-bit high-speed low-power ADC with

internal reference regulator

Preliminary specification

TDA8764

SYMBOL

PARAMETER

CONDITIONS

TWO-TONE; note 9

TTID

two-tone intermodulation distortion

BIT ERROR RATE

BER

bit error rate

fclk = 40 MHz

fclk = 80 MHz

fi = 5 MHz; Vi = ±16 LSB at

code 512

fclk = 40 MHz

MIN.

−

−

−

fclk = 80 MHz

−

Timing (fclk = 40 MHz; CL = 10 pF) /4 version; see Fig.5 and note 10

tds

sampling delay time

−

th

output hold time

5

td

output delay time

VCCO = 2.7 V

tbf

VCCO = 3.3 V

tbf

CL

digital output load capacitance

−

SR

slew rate

VCCO = 2.7 V; CL = 10 pF −

Timing (fclk = 80 MHz; CL = 10 pF) /8 version; see Fig.5 and note 10

tds

sampling delay time

−

th

output hold time

4

td

output delay time

VCCO = 2.7 V

tbf

VCCO = 3.3 V

tbf

CL

digital output load capacitance

−

SR

slew rate

VCCO = 2.7 V; CL = 10 pF

−

3-state output delay times (fclk = 40 MHz) /4 version; see Fig.6

tdZH

enable HIGH

−

tdZL

enable LOW

−

tdHZ

disable HIGH

−

tdLZ

disable LOW

−

3-state output delay times (fclk = 80 MHz) /8 version; see Fig.6

tdZH

enable HIGH

−

tdZL

enable LOW

−

tdHZ

disable HIGH

−

tdLZ

disable LOW

−

TYP. MAX. UNIT

tbf

−

dB

tbf

−

dB

10−13 −

10−13 −

times/

sample

times/

sample

−

2

ns

−

−

ns

12

tbf

ns

11

tbf

ns

−

10

pF

−

tbf

V/µs

−

2

ns

−

−

ns

8

tbf

ns

7

tbf

ns

−

10

pF

−

tbf

V/µs

tbf

tbf

ns

tbf

tbf

ns

tbf

tbf

ns

tbf

tbf

ns

tbf

tbf

ns

tbf

tbf

ns

tbf

tbf

ns

tbf

tbf

ns

1999 Jan 12

12

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