TDA8764HL 查看數據表（PDF） - Philips Electronics

零件编号

产品描述 (功能)

生产厂家

TDA8764HL

10-bit high-speed low-power ADC with internal reference regulat

Philips Electronics 

Philips Semiconductors

10-bit high-speed low-power ADC with

internal reference regulator

Preliminary specification

TDA8764

Notes

1. In addition to a good layout of the digital and analog ground, it is recommended that the rise and fall times of the clock

must not be less than 0.5 ns.

2.

The input

admittance is

Vi=





R--1--i

+

C

i

j

w

3. Analog input voltages producing code 0 up to and including code 1023:

a) Voffset(B) (offset voltage BOTTOM) is the difference between the analog input which produces data equal to 00

and the reference voltage BOTTOM (VRB) at Tamb = 25 °C.

b) Voffset(T) (offset voltage TOP) is the difference between reference voltage TOP (VRT) and the analog input which

produces data outputs equal to code 1023 at Tamb = 25 °C.

4. In order to ensure the optimum linearity performance of such converter architecture the lower and upper extremities

of the converter reference resistor ladder (corresponding to output codes 0 and 1023 respectively) are connected to

pins VRB and VRT via offset resistors ROB and ROT as shown in Fig.4.

a) The current flowing into the resistor ladder is IL= R-----O---V-B---R-+---T--R--–---L--V--+--R---R-B---O----T- and the full-scale input range at the converter,

to cover code 0 to code 1023, is VI = RL × IL= R-----O----B----+-----RR-----LL----+-----R----O----T- × (VRT – VRB) = 0.866 × (VRT – VRB)

b) Since RL, ROB and ROT have similar behaviour with respect to process and temperature variation, the ratio

R-----O----B----+-----RR-----LL----+-----R----O----T- will be kept reasonably constant from device to device. Consequently variation of the output

codes at a given input voltage depends mainly on the difference VRT − VRB and its variation with temperature and

supply voltage. When several ADCs are connected in parallel and fed with the same reference source, the

matching between each of them is then optimized.

5.

EG = --(--V----1---0--2---3----–V----V-i--(--0p--)-–----p–---)-V-----i--(--p---–----p---) × 100

6. The analog bandwidth is defined as the maximum input sine wave frequency which can be applied to the device.

No glitches greater than 2 LSBs, nor any significant attenuation are observed in the reconstructed signal.

7. The analog input settling time is the minimum time required for the input signal to be stabilized after a sharp full-scale

input (square wave signal) in order to sample the signal and obtain correct output data.

8. Effective bits are obtained via a Fast Fourier Transform (FFT) treatment taking 8 K acquisition points per equivalent

fundamental period. The calculation takes into account all harmonics and noise up to half of the clock frequency

(NYQUIST frequency). Conversion to signal-to-noise ratio: SINAD = EB × 6.02 + 1.76 dB.

9. Intermodulation measured relative to either tone with analog input frequencies of 5 and 5.1 MHz. The two input

signals have the same amplitude and the total amplitude of both signals provides full-scale to the converter.

10. Output data acquisition: the output data is available after the maximum delay time of td(max). For the 80 MHz version

it is recommended to have the lowest possible output load.

1999 Jan 12

13

Share Link: