TDA8315T 查看數據表（PDF） - Philips Electronics

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TDA8315T

Integrated NTSC decoder and sync processor

Philips Electronics 

Philips Semiconductors

Integrated NTSC decoder

and sync processor

Preliminary specification

TDA8315T

13. The horizontal output pulses are obtained from the horizontal oscillator by a pulse shaper. The width of the output

pulse is approximately 5.4 µs and the rising edge of the pulse symmetrically coincides with the start of the sync pulse

at the input.

14. The vertical output pulses are generated by a divider circuit. The vertical output pulse has a delay of 37.5 µs with

respect to the start of the vertical sync pulse at the input. This is caused by the clock frequency of the divider being

twice the horizontal frequency.

This divider circuit has 2 modes of operation:

Search mode (large window).

This mode is switched on when the circuit is not synchronized or, when a non-standard signal is received (the number

of lines per frame outside the range is between 261 and 264). In the search mode the divider can be triggered

between line 244 and line 288 (approximately 54 to 64.5 Hz).

Standard mode (narrow window).

This mode is switched on when more than 15 successive vertical sync pulses are detected in the narrow window.

When the circuit is in the standard mode and a vertical sync pulse is missing the output pulse is generated at the end

of the window. Consequently, the disturbance of the picture is very small. The circuit will switch back to the search

window when, for 6 successive vertical periods, no sync pulses are found within the window. When no input signal

is available the divider generates output pulses with a timing of 262.5 lines (standard 60 Hz signal).

Table 1 Output current of phase detector.

CURRENT PHASE DETECTOR DURING

Weak signal and synchronized

Strong signal and synchronized

Not synchronized

Note

1. Vertical retrace.

SCAN (µA)

30

180

180

VERTICAL RETRACE (µA)

30

270

270

GATED YES/NO

YES (5.7 µs)

YES (12 µs)(1)

NO

QUALITY SPECIFICATION

Quality level in accordance with SNW-FQ-611-part E.

SYMBOL

ESD

PARAMETER

protection circuit specification (note 1)

RANGE A(2)

>2 000

100

1 500

Notes

1. All pins are protected against ESD by means of internal clamping diodes.

2. Range A is for Human body model.

3. Range B is for machine model.

Latch up

All pins meet the specification:

Itrigger ≥ 100 mA or ≥ 1.5 VDDmax

Itrigger ≤ −100 mA or ≤ −0.5 VDDmax.

RANGE B(3)

>200

200

0

UNIT

V

pF

Ω

September 1994

11

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