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TGA4953-SL 查看數據表(PDF) - TriQuint Semiconductor

零件编号
产品描述 (功能)
生产厂家
TGA4953-SL
TriQuint
TriQuint Semiconductor TriQuint
TGA4953-SL Datasheet PDF : 19 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
Parameter
TABLE III
RF CHARACTERIZATION TABLE
(TA = 25°C, Nominal)
Product Datasheet
Jan 4, 2012
TGA4953-SL
Test Conditions
Min
Typ Max Units Notes
Eye Amplitude
Additive Jitter
(RMS)
VD2T = 8.0V
VD2T = 6.5V
VD2T = 5.5V
VD2T = 4.5V
VD2T = 4.0V
VIN = 500mVPP
VIN = 800mVPP
10
8.0
7.0
VPP 3/ 4/
6.0
5.5
0.9
1.0
2.0
2.0
Ps
5/
Q-Factor
VIN = 500mVPP
VIN = 800mVPP
28.5
35
28.5
35
V/V
Delta Eye
Amplitude
| 500–800 mV in p-p| -0.10
0.10 VPP
Delta Crossing
Percentage
| 500–800 mV in p-p|
-6
6
%
Table III Notes:
1/ Verified at package level RF test
2/ Typical Package RF Test Bias Conditions: Vdd = 5V, adjust VG1 to achieve Idd = 65mA then
adjust VG2 to achieve ID2T = 115 – 155 mA (Idd = 180 - 220mA), VCTRL1 = -0.2V & VCTRL2 =
+0.2 V
3/ Verified by design, SMT assembled onto a demonstration board detailed on sheet 6.
4/ VIN = 250mV, Data Rate = 10.7Gb/s, VD1 = VD2T or greater, VCTRL2 and VG2 are adjusted for
maximum output. Typical final Idd under drive ~ 220 mA.
5/ Computed using RSS Method where JRMS_DUT = (JRMS_TOTAL2 - JRMS_SOURCE2)
6/ Verified at die level on-wafer probe
7/ Power Bias Die Probe: VTEE = 8V, adjust VG to achieve Idd = 175mA ±5%, VCTRL = +1.5V
Note: At the die level, drain bias is applied through the RF output port using a bias tee, voltage
is at the DC input to the bias tee
TriQuint Semiconductor: www. triquint.com (972)994-8465 Fax (972)994-8504 info-networks@tqs.com 5

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