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TC7650CPD

Chopper Stabilized Operational Amplifier

Microchip Technology 

TC7650

positive duty cycle is desired for frequencies above

500Hz to ensure transients settle before the internal

switches open.

The external clock input can also be used as a strobe

input. If a strobe signal is connected at the external

clock input so that it is LOW during the time an overload

signal is applied, neither capacitor will be charged. The

leakage currents at the capacitors pins are very low. At

25°C a typical TC7650 will drift less than 10V/sec.

3.6 Output Clamp

Chopper-stabilized systems can show long recovery

times from overloads. If the output is driven to either

supply rail, output saturation occurs. The inputs are no

longer held at a "virtual ground." The VOS null circuit

treats the differential signal as an offset and tries to cor-

rect it by charging the external capacitors. The nulling

circuit also saturates. Once the input signal returns to

normal, the response time is lengthened by the long

recovery time of the nulling amplifier and external

capacitors.

Through an external clamp connection, the TC7650

eliminates the overload recovery problem by reducing

the feedback network gain before the output voltage

reaches either supply rail.

FIGURE 3-3:

INTERNAL CLAMP CIRCUIT

Internal

Positive Clamp Bias ≈ V+ - VT ≈ V+ - 0.7

P-Channel

Output

Clamp Pin

N-Channel

FIGURE 3-4:

*Connect To VSS

On 8-Pin DIP.

NON-INVERTING AMPLIFIER

WITH OPTIONAL CLAMP

0.1µF

Input

C*

+R

TC7650 C

R3 + (R1/R2) ‡ 100 kΩ

For Full Clamp Effect

Clamp

R3

Output

R2

R1

FIGURE 3-5:

INVERTING AMPLIFIER WITH

OPTIONAL CLAMP

R2

Clamp

R1

Input

*Connect To VR–

On 8-Pin DIP.

TC7650 C

+ R*

C

Output

(R1 R2) ‡ 100 kΩ

For Full Clamp

Effect

0.1 µF 0.1 µF

The output clamp circuit is shown in Figure 3-3, with

typical inverting and non-inverting circuit connections

shown in Figures 3-4 and 3-5. Output voltage versus

clamp circuit current characteristics are shown in the

typical operating curves. For the clamp to be fully effec-

tive, the impedance across the clamp output should be

greater than 100k.

3.7 Latch-Up Avoidance

Junction-isolated CMOS circuits inherently include a

parasitic 4-layer (p-n-p-n) structure which has charac-

teristics similar to an SCR. Under certain circum-

stances this junction may be triggered into a low-

impedance state, resulting in excessive supply current.

To avoid this condition, no voltage greater than 0.3V

beyond the supply rails should be applied to any pin. In

general, the amplifier supplies must be established

either at the same time or before any input signals are

applied. If this is not possible, the drive circuits must

limit input current flow to under 0.1mA to avoid latch-

up.

3.8 Thermoelectric Potentials

Precision DC measurements are ultimately limited by

thermoelectric potentials developed in thermocouple

junctions of dissimilar metals, alloys, silicon, etc.

Unless all junctions are at the same temperature, ther-

moelectric voltages, typically around 0.1V/°C, but up

to tens of V/°C for some materials, will be generated.

In order to realize the benefits extremely-low offset volt-

ages provide, it is essential to take special precautions

to avoid temperature gradients. All components should

be enclosed to eliminate air movement, especially

those caused by power dissipating elements in the sys-

tem. Low thermoelectric co-efficient connections

should be used where possible and power supply volt-

ages and power dissipation should be kept to a mini-

mum. High impedance loads are preferable, and

separation from surrounding heat dissipating elements

is advised.

DS21463C-page 6

 2001-2012 Microchip Technology Inc.

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