ICL7650CPA 查看數據表（PDF） - Linear Technology
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ICL7650CPA Datasheet PDF : 24 Pages
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LTC1052/LTC7652
TYPICAL PERFOR A CE CHARACTERISTICS
Response Time vs Overdrive
{INPUT
VREF + OVERDRIVE
VREF – 1mV
{ 5V
OUTPUT
50µV
–5V
10µV
5µV
20ms/DIV
TEST CIRCUITS
Electrical Characteristics Test Circuit (TC1)
R2
1M
R1
V+
1k
2–
7
6
LTC1052
3+
8
4
1
0.1µF
0.1µF
OUTPUT
RL
V–
LTC1052/7652 • TC01
DC to 10Hz and DC to 1HZ Noise Test Circuit (TC3)
C2
C3
R2
R4
V+
2– 7
R3
6
R1
LTC1052
3+
8
4
1
0.1µF
0.1µF
3+
C4
LT1001
2–
34k
6 OUTPUT
(NOISE x 20,000)
34k
V–
BANDWIDTH R1
R2
10Hz
16.2Ω 162k
1Hz
16.2Ω 162k
R3
16.2k
162k
R4
16.2k
162k
C2
0.1µF
1.0µF
C3
1.0µF
1.0µF
C4
1.0µF
1.0µF
LTC1052/7652 • TC02
U
THEORY OF OPERATIO
DC OPERATION
The shaded portion of the LTC1052 block diagram
(Figure 1a) entirely determines the amplifier’s DC
characteristics. During the auto zero portion of the cycle,
the gm1 inputs are shorted together and a feedback path is
closed around the input stage to null its offset. Switch S2
and capacitor CEXTA act as a sample-and-hold to store the
nulling voltage during the next step—the sampling cycle.
In the sampling cycle, the zeroed amplifier is used to
amplify the differential input voltage. Switch S2 connects
the amplified input voltage to CEXTB and the output gain
6
stage. CEXTB and S2 act as a sample-and-hold to store the
amplified input signal during the auto zero cycle.
By switching between these two states at a frequency
much higher than the signal frequency, a continuous
output results.
Notice that during the auto zero cycle the gm1 inputs are
not only shorted together, but are also shorted to the
inverting input. This forces nulling with the common mode
voltage present and accounts for the extremely high
CMRR of the LTC1052. In the same fashion, variations in
1052fa
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