SM8702AM 查看數據表（PDF） - Nippon Precision Circuits
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SM8702AM Datasheet PDF : 16 Pages
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SM8702AM
PCI clock characteristics
Ta = 0 to 70°C, VDD = 3.3V ± 5%, VSS = 0V, fX’tal = 14.318MHz, CL = 30pF unless otherwise noted.
Parameter
Output clock rise time1
Output clock fall time1
Duty cycle
Output clock jitter1
Output clock skew 1
Symbol
Condition
tr
VOL = 0.8V → VOH = 2.4V transition time
tf
VOH = 2.4V → VOL = 0.8V transition time
Dt VT = 1.5V
tjc V T = 1.5V, rising edge Cycle-to-cycle jitter
Between PCI clocks:
tskw V T = 1.5V, rising edge PCICLK_F and
PCICLK[0:4]
Rating
Unit
min
typ
max
–
–
2.0
ns
–
–
2.0
ns
45
50
55
%
–
–
250
ps
–
–
250
ps
CPU/PCI clock skew 2
V T- C P U C L K = 1.25/1.5V, B e t ween CPU and PCI
thpsk V T-PCICLK = 1.5V, rising clocks: CPUCLK[0:1] and
1.0
2.2
4.0
ns
edges
PCICLK_F/PCICLK[0:4]
Clock frequency stabilize time1
Output impedance3
tstb Cold start
ZO
VO = 0.5VDD
Supply ON (VDD = 3.3V)
until clock reaches
–
–
3
ms
specified frequency
10
–
60
Ω
1. Design maximum values, not 100% guaranteed.
2. CPUCLK and PCICLK r ising edges, V T-CPUCLK = 1.25V (VD D L = 2.5V)/1.5V (VD D L = 3.3V), V T-PCICLK = 1.5V skew measurement.
3. Design estimate values, not 100% guaranteed.
SDRAM clock characteristics
Ta = 0 to 70°C, VDD = VDDL = 3.3V ± 5%, VSS = 0V, fX’tal = 14.318MHz, CL = 30pF unless otherwise noted.
Parameter
Output clock rise time1
Output clock fall time1
Duty cycle1
Symbol
Condition
Rating
Unit
min
typ
max
tr
VOL = 0.8V → VOH = 2.4V transition time
–
–
2.0
ns
tf
VOH = 2.4V → VOL = 0.8V transition time
–
–
2.0
ns
Dt
V T = 1.5V, BU F F E R I N
input clock signal rise
and fall time rate ≥ 1V/ns
3.3V BUFFERIN input
clock signal logic level
40
50
60
%
Output clock skew 1
V T = 1.5V, rising edge,
ts k w
BUFFERIN input clock Between SDRAM clocks:
signal rise and fall time SDRAM[0:13]
–
rate ≥ 1V/ns
200
600
ps
Input to output propagation
delay2,3
Output impedance3
V T-BU F F E R I N = 1.5V,
tp d
V T- S D R A M = 1.5V, rising
edges, BUFFERIN input
clock signal rise and fall
Between BUFFERIN and
SDRAM[0:13]
–
time rate ≥ 1V/ns
5.5
7.0
ns
ZO
VO = 0.5VDD
10
–
60
Ω
1. Design maximum values, not 100% guaranteed.
2. B UFFERIN and SDRAM r ising edges, V T-BUFFERIN = 1.5V (logic level = 3.3V), V T- S D R A M = 1.5V delay measurement.
3. Design estimate values, not 100% guaranteed.
NIPPON PRECISION CIRCUITS—8
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