LH540204 查看數據表（PDF） - Sharp Electronics

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LH540204

CMOS 4096 × 9 Asynchronous FIFO

Sharp Electronics 

LH540204

CMOS 4096 × 9 Asynchronous FIFO

AC ELECTRICAL CHARACTERISTICS 1 (Over Operating Range)

SYMBOL

PARAMETER

tA = 20 ns

MIN MAX

tA = 25 ns

MIN MAX

READ CYCLE TIMING

tRC

tA

tRR

tRPW

tRLZ

tWLZ

tDV

tRHZ

Read Cycle Time

Access Time

Read Recovery Time

Read Pulse Width 2

Data Bus Active from Read LOW 3

Data Bus Active from Write HIGH 3,4

Data Held Valid from Read Pulse HIGH

Data Bus High-Z from Read HIGH 3

30 – 35 –

– 20 – 25

10 – 10 –

20 – 25 –

5

–

5

–

10 – 10 –

5

–

5

–

– 15 – 15

WRITE CYCLE TIMING

tWC

tWPW

tWR

tDS

tDH

Write Cycle Time

Write Pulse Width 2

Write Recovery Time

Data Setup Time

Data Hold Time

30 – 35 –

20 – 25 –

10 – 10 –

12 – 15 –

0

–

0

–

RESET TIMING

tRSC

tRS

tRSR

tRRSS

tWRSS

Reset Cycle Time

Reset Pulse Width 2

Reset Recovery Time

Read HIGH to RS HIGH

Write HIGH to RS HIGH

30 – 35 –

20 – 25 –

10 – 10 –

20 – 25 –

20 – 25 –

RETRANSMIT TIMING 5

tRTC

Retransmit Cycle Time

tRT

Retransmit Pulse Width 2

tRTR

Retransmit Recovery Time

30 – 35 –

20 – 25 –

10 – 10 –

FLAG TIMING

tEFL

Reset LOW to Empty Flag LOW

– 30 – 35

tHFH,FFH Reset LOW to Half-Full and Full Flags HIGH –

30

–

35

tREF

Read LOW to Empty Flag LOW

– 20 – 25

tRFF

Read HIGH to Full Flag HIGH

– 20 – 25

tWEF

Write HIGH to Empty Flag HIGH

– 20 – 25

tWFF

Write LOW to Full Flag LOW

– 20 – 25

tWHF

Write LOW to Half-Full Flag LOW

– 20 – 25

tRHF

Read HIGH to Half-Full Flag HIGH

– 20 – 25

EXPANSION TIMING

tXOL

Expansion Out LOW

tXOH

Expansion Out HIGH

tXI

Expansion In Pulse Width

tXIR

Expansion In Recovery Time

tXIS

Expansion in Setup Time

– 20 – 25

– 20 – 25

20 – 25 –

10 – 10 –

10 – 10 –

NOTES:

1. All timing measurements are performed at ‘AC Test Condition’ levels.

2. Pulse widths less than minimum value are not allowed.

3. Values are guaranteed by design; not currently tested.

4. Only applies to read-data flow-through mode.

5. See also Note 2, Figure 19.

tA = 35 ns

MIN MAX

45 –

– 35

10 –

35 –

5

–

10 –

5

–

– 15

45 –

35 –

10 –

18 –

0

–

45 –

35 –

10 –

35 –

35 –

45 –

35 –

10 –

– 45

– 45

– 35

– 35

– 35

– 35

– 35

– 35

– 35

– 35

35 –

10 –

15 –

tA = 50 ns UNIT

MIN MAX

65 – ns

– 50 ns

15 – ns

50 – ns

5

– ns

10 – ns

5

– ns

– 20 ns

65 – ns

50 – ns

15 – ns

30 – ns

0

– ns

65 – ns

50 – ns

15 – ns

50 – ns

50 – ns

65 – ns

50 – ns

15 – ns

– 65 ns

– 65 ns

– 45 ns

– 45 ns

– 45 ns

– 45 ns

– 45 ns

– 45 ns

– 50 ns

– 50 ns

50 – ns

10 – ns

15 – ns

10

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