LH540204 查看數據表（PDF） - Sharp Electronics
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LH540204 Datasheet PDF : 18 Pages
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CMOS 4096 × 9 Asynchronous FIFO
TIMING DIAGRAMS
tRSC
tRS
RS
R,W
EF
t RRSS
t WRSS
tEFL
tRSR
tFFH , tHFH
FF,HF
NOTES:
1. tRSC = tRS + tRSR.
2. W and R ≥ VIH around the rising edge of RS.
3. The Data Out pins (D0 - D8) are forced into a
high-impedance state whenever EF = LOW.
Figure 10. Reset Timing
R
Q0 - Q8
W
D0 - D8
tRC
tA
tRR
t RPW
tA
t RLZ
t DV
VALID DATA OUT
t WPW
t WC
t WR
t RHZ
VALID DATA OUT
t DS
t DH
VALID DATA IN
VALID DATA IN
Figure 11. Asynchronous Write and Read Operation
LH540204
540204-14
540204-5
11
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