LH540204 查看數據表（PDF） - Sharp Electronics
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LH540204 Datasheet PDF : 18 Pages
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LH540204
FEATURES
• Fast Access Times: 20/25/35/50 ns
• Fast-Fall-Through Time Architecture Based on
CMOS Dual-Port SRAM Technology
• Input Port and Output Port Have Entirely
Independent Timing
• Expandable in Width and Depth
• Full, Half-Full, and Empty Status Flags
• Data Retransmission Capability
• TTL-Compatible I/O
• Pin and Functionally Compatible with Sharp LH5499
and with Am/IDT/MS7204
• Control Signals Assertive-LOW for Noise Immunity
• Packages:
28-Pin, 300-mil PDIP
28-Pin, 300-mil SOJ *
32-Pin PLCC
PIN CONNECTIONS
28-PIN PDIP
28-PIN SOJ * W 1
D8 2
D3 3
D2 4
D1 5
D0 6
XI 7
FF 8
Q0
9
Q1 10
Q2 11
Q3 12
Q8 13
VSS 14
TOP VIEW
28 VCC
27 D4
26 D5
25 D6
24 D7
23 FL/RT
22 RS
21 EF
20 XO/HF
19 Q7
18 Q6
17 Q5
16 Q4
15 R
540204-2D
Figure 1. Pin Connections for PDIP and
SOJ * Packages
CMOS 4096 × 9 Asynchronous FIFO
FUNCTIONAL DESCRIPTION
The LH540204 is a FIFO (First-In, First-Out) memory
device, based on fully-static CMOS dual-port SRAMtech-
nology, capable of storing up to 4096 nine-bit words. It
follows the industry-standard architecture and package
pinouts for nine-bit asynchronous FIFOs. Each nine-bit
LH540204 word may consist of a standard eight-bit byte,
together with a parity bit or a block-marking/framing bit.
The input and output ports operate entirely inde-
pendently of each other, unless the LH540204 becomes
either totally full or else totally empty. Data flow at a port
is initiated by asserting either of two asynchronous, as-
sertive-LOW control inputs: Write (W) for data entry at the
input port, or Read (R) for data retrieval at the output port.
Full, Half-Full, and Empty status flags monitor the
extent to which the internal memory has been filled. The
system may make use of these status outputs to avoid
the risk of data loss, which otherwise might occur either
by attempting to write additional words into an already-full
LH540204, or by attempting to read additional words from
an already-empty LH540204. When an LH540204 is
operating in a depth-cascaded configuration, the Half-Full
Flag is not available.
32-PIN PLCC
TOP VIEW
4 3 2 1 32 31 30
D2
5
D1
6
D0
7
XI 8
29 D6
28 D7
27 NC
26 FL/RT
FF 9
25 RS
Q0 10
24 EF
Q1 11
23 XO/HF
NC 12
22 Q7
Q2 13
21 Q6
14 15 16 17 18 19 20
NOTE: * = No external electrical connections are allowed.
540204-3D
Figure 2. Pin Connections for PLCC Package
* This is a final data sheet; except that all references to the SOJ package have Advance Information status.
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