CGS3321CW 查看數據表（PDF） - Fairchild Semiconductor

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CGS3321CW

CMOS Crystal Clock Generators

Fairchild Semiconductor 

Pin Descriptions

Note: Pin out varies for each device.

OSC_IN Input to Oscillator Inverter. The output of the

crystal would be connected here.

OEH

OSC_OUT Resistive Buffered Output of the Oscillator

Inverter

DIVB

(CGS3322 only)

3-Level input used to select Binary Divide-by

value of output frequency.

DC_ADJ

(CGS3321 only)

Active high input that controls output duty

cycle. Logic high level will delay the HL transi-

tion edge approximately 0.3 ns.

OUT

OSCLO_1

VCC

GND

Note: Pin out varies for each device.

Block Diagrams

Active HIGH 3-STATE enable pin. This pin pulls

to a HIGH value when left floating and 3-

STATEs the output when forced LOW. This pin

has TTL compatible input levels.

This pin is the main clock output on the device.

The Oscillator LOW pin is the ground for the

Oscillator.

The power pin for the chip.

The ground pin for all sections of the circuitry

except the oscillator and oscillator related

circuitry.

Note: Pin numbers vary for each device

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