GM71VS17403CT-7 查看數據表（PDF） - Hynix Semiconductor

零件编号

产品描述 (功能)

生产厂家

GM71VS17403CT-7

4,194,304 WORDS x 4 BIT CMOS DYNAMIC RAM

Hynix Semiconductor 

Self Refresh Mode ( L-version )

Symbol

Parameter

tRASS

tRPS

tCHS

RAS Pulse Width ( Self-refresh )

RAS Precharge Time ( Self-refresh )

CAS Hold Time ( Self-refresh )

GM71V17403C

GM71VS17403CL

GM71VS17403 GM71VS17403 GM71VS17403

CL-5

CL-6

CL-7

Min Max Min Max Min Max

Unit

100 - 100 - 100 -

µs

90 - 110 - 130 -

ns

-50 - -50 - -50 -

ns

Note

Notes:

1. AC Measurements assume tT = 2ns.

2. An initial pause of 200us is required after power up followed by a minimum of eight

initialization cycles (any combination of cycles containing RAS-only refresh or CAS-before-

RAS refresh). If the internal refresh counter is used, a minimum of eight CAS-before-RAS

refresh cycles are required.

3. Operation with the tRCD(max) limit insures that tRAC(max) can be met, tRCD(max) is specified as a

reference point only; if tRCD is greater than the specified tRCD(max) limit, then access time is

controlled exclusively by tCAC.

4. Operation with the tRAD(max) limit insures that tRAC(max) can be met, tRAD(max) is specified as a

reference point only; if tRAD is greater than the specified tRAD(max) limit, then access time is

controlled exclusively by tAA.

5. Either tODD or tCDD must be satisfied.

6. Either tDZO or tDZC must be satisfied.

7. VIH(min) and VIL(max) are reference levels for measuring timing of input signals. Also,

transition times are measured between VIH(min) and VIL(max).

8. Assume that tRCD<=tRCD(max) and tRAD<=tRAD(max). If tRCD or tRAD is greater than the maximum

recommended value shown in this table, tRAC exceeds the value shown.

9. Measured with a load circuit equivalent to 1 TTL loads and 100pF.

10. Assume that tRCD >=tRCD(max) and tRCD + tCAC(max) >= tRAD + tAA(max).

11. Assume that tRAD >=tRAD(max) and tRCD + tCAC(max) <= tRAD + tAA(max).

12. Either tRCH or tRRH must be satisfied for a read cycles.

13. tOFF(max) and tOEZ(max) define the time at which the outputs achieve the open circuit condition

and are not referenced to output voltage levels.

Rev 0.1 / Apr’01

Share Link: