DatasheetQ Logo
Electronic component search and free download site. Transistors,MosFET ,Diode,Integrated circuits

42754G 查看數據表(PDF) - Infineon Technologies

零件编号
产品描述 (功能)
生产厂家
42754G
Infineon
Infineon Technologies Infineon
42754G Datasheet PDF : 29 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
4.3
Thermal Resistance
TLE42754
General Product Characteristics
Table 3 Thermal Resistance
Parameter
Symbol
Values
Unit Note / Test Condition
Number
Min. Typ. Max.
TLE42754D (PG-TO252-5)
Junction to Case1)
Junction to Ambient1)
Junction to Ambient1)
RthJC
RthJA
RthJA
Junction to Ambient1)
RthJA
Junction to Ambient1)
RthJA
3.7
27
110 –
57
42
K/W –
P_4.3.1
K/W FR4 2s2p board2)
P_4.3.2
K/W FR4 1s0p board, footprint P_4.3.3
only3)
K/W FR4 1s0p board, 300 mm2 P_4.3.4
heatsink area on PCB3)
K/W FR4 1s0p board, 600 mm2 P_4.3.5
heatsink area on PCB3)
TLE42754G (PG-TO263-5)
Junction to Case1)
Junction to Ambient1)
Junction to Ambient1)
RthJC
RthJA
RthJA
Junction to Ambient1)
RthJA
Junction to Ambient1)
RthJA
3.7
22
70
42
33
K/W –
P_4.3.6
K/W FR4 2s2p board2)
P_4.3.7
K/W FR4 1s0p board, footprint P_4.3.8
only3)
K/W FR4 1s0p board, 300 mm2 P_4.3.9
heatsink area on PCB3)
K/W FR4 1s0p board, 600 mm2 P_4.3.10
heatsink area on PCB3)
TLE42754E (PG-SSOP-14 exposed pad)
Junction to Case1)
Junction to Ambient1)
Junction to Ambient1)
RthJC
RthJA
RthJA
7
43
120 –
K/W –
P_4.3.11
K/W FR4 2s2p board2)
P_4.3.12
K/W FR4 1s0p board, footprint P_4.3.13
only3)
Junction to Ambient1)
RthJA
59
K/W FR4 1s0p board, 300 mm2 P_4.3.14
heatsink area on PCB3)
Junction to Ambient1)
RthJA
49
K/W FR4 1s0p board, 600 mm2 P_4.3.15
heatsink area on PCB3)
1) not subject to production test, specified by design
2) Specified RthJA value is according to Jedec JESD51-2,-5,-7 at natural convection on FR4 2s2p board; The Product
(Chip+Package) was simulated on a 76.2 x 114.3 x 1.5 mm³ board with 2 inner copper layers (2 x 70µm Cu, 2 x 35µm Cu).
Where applicable a thermal via array under the exposed pad contacted the first inner copper layer.
3) Specified RthJA value is according to JEDEC JESD 51-3 at natural convection on FR4 1s0p board; The Product
(Chip+Package) was simulated on a 76.2 × 114.3 × 1.5 mm3 board with 1 copper layer (1 x 70µm Cu).
Data Sheet
9
Rev. 1.2, 2014-07-03

Share Link: 

datasheetq.com  [ Privacy Policy ]Request Datasheet ] [ Contact Us ]