24C64 查看數據表（PDF） - Turbo IC Inc

零件编号

产品描述 (功能)

生产厂家

24C64

CMOS I²C 2-WIRE BUS 64K ELECTRICALLY ERASABLE PROGRAMMABLE ROM 8K X 8 BIT EEPROM

Turbo IC Inc 

Turbo IC, Inc.

24C64

DESCRIPTION (Continued)

For a write operation, the master issues a start condition,

device address byte, 2 memory address bytes, and then up

to 32 data bytes. The Turbo IC 24C64 acknowledges after

each byte transmission. To terminate the transmission, the

master issues a stop condition by pulling SDA from low to

high while SCL is high.

For a read operation, the master issues a start condition and

a device address byte. The Turbo IC 24C64 acknowledges,

and then transmits a data byte, which is accessed from the

EEPROM memory.The master acknowledges, indicating that

it requires more data bytes. The Turbo IC 24C64 transmits

more data bytes, with the memory address counter auto-

matically incrementing for each data byte, until the master

does not acknowledge, indicating that it is terminating the

transmission. The master then issues a stop condition.

DEVICE OPERATION:

BIDIRECTIONAL BUS PROTOCOL:

The Turbo IC 24C64 follows the extended I²C bus protocol.

The protocol defines any device that sends data onto the

SDA bus as a transmitter, and the receiving device as a re-

ceiver. The device controlling the transfer is the master and

the device being controlled is the slave. The master always

initiates the data transfers, and provides the clock for both

transmit and receive operations. The Turbo IC 24C64 acts as

a slave device in all applications. Either the master or the

slave can take control of the SDA bus, depending on the

requirement of the protocol.

ACKNOWLEDGE:

All data is serially transmitted in bytes (8 bits) on the SDA

bus. The acknowledge protocol is used as a handshake sig-

nal to indicate successful transmission of a byte of data. The

bus transmitter, either the master or the slave (Turbo IC

24C64), releases the bus after sending a byte of data on the

SDA bus. The receiver pulls the SDA bus low during the ninth

clock cycle to acknowledge the successful transmission of a

byte of data. If the SDA is not pulled low during the ninth

clock cycle, the Turbo IC 24C64 terminates the data trans-

mission and goes into standby mode.

START/STOP CONDITION AND DATA TRANSITIONS:

While SCL clock is high, a high to low transition on the SDA

bus is recognized as a START condition which precedes any

read or write operation. While SCL clock is high, a low to

high transition on the SDA bus is recognized as a STOP con-

dition which terminates the communication and places the

Turbo IC 24C64 into standby mode. All other data transitions

on the SDA bus must occur while SCL clock is low to ensure

proper operation.

For the write operation, the Turbo IC 24C64 acknowledges

after the device address byte, acknowledges after each

memory address byte, and acknowledges after each subse-

quent data byte.

For the read operation, the Turbo IC 24C64 acknowledges

after the device address byte. Then the Turbo IC 24C64 trans-

mits each subsequent data byte, and the master acknowl-

edges after each data byte transfer, indicating that it requires

more data bytes. The Turbo IC 24C64 monitors the SDA bus

for the acknowledge. To terminate the transmission, the mas-

ter does not acknowledge, and then sends a stop condition.

Write Cycle Timing

SCL

SDA

8th BIT ACK

WORD n

tWC

STOP

CONDITION

START

CONDITION

Note: The write cycle time tWC is the time from a valid stop condition of a write sequence to the end of the internal clear / write cycle.

2

Share Link: