AM79C90 查看數據表（PDF） - Advanced Micro Devices
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AM79C90 Datasheet PDF : 62 Pages
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PRELIMINARY
READ
(Input/Output, Three-State)
Indicates the type of operation to be performed in the
current bus cycle. This signal is an output when the
C-LANCE is a Bus Master.
High — Data is taken off the DAL lines by the
C-LANCE.
Low — Data is placed on the DAL lines by the
C-LANCE.
The signal is an input when the C-LANCE is a Bus
Slave.
High — Data is placed on the DAL lines by the
C-LANCE.
Low — Data is taken off the DAL lines by the
C-LANCE.
READY
(Input/Output, Open Drain)
When the C-LANCE is a Bus Master, READY is an
asynchronous acknowledgment from the bus memory
that it will accept data in a WRITE cycle or that it has
put data on the DAL lines in a READ cycle.
As a Bus Slave, the C-LANCE asserts READY when it
has put data on the DAL lines during a READ cycle or
is about to take data off the DAL lines during a write
cycle. READY is a response to DAS and will return High
after DAS has gone High. READY is an input when the
C-LANCE is a Bus Master and an output when the
C-LANCE is a Bus Slave.
RENA
Receive Enable (Input)
A logical input that indicates the presence of carrier on
the channel.
RESET
Reset (Input)
Reset causes the C-LANCE to cease operation, clear
its internal logic, force all three-state buffers to the high-
impedance state, and enter an idle state with the stop
bit of CSR0 set. It is recommended that a 3.3 kΩ pullup
resistor be connected to this pin.
RX
Receive (Input)
Receive Input Bit Stream.
TCLK
Transmit Clock (Input)
10 MHz clock.
TENA
Transmit Enable (Output)
Transmit Output Bit Stream enable. When asserted, it
enables valid transmit output (TX).
TX
Transmit (Output)
Transmit Output Bit Stream.
VDD
Power Supply Pin +5 V ±5%
It is recommended that 0.1 µF and 10 µF decoupling
capacitors be used between VDD and VSS.
VSS
Ground
Pin 1 and 24 (48-Pin DlPs) should be connected
together externally, as close to the chip as possible.
Am79C90
7
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