STK12C68-5SF55I 查看數據表（PDF） - Simtek Corporation
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STK12C68-5SF55I Datasheet PDF : 13 Pages
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STK12C68
SRAM READ CYCLES #1 & #2
SYMBOLS
NO.
#1, #2
Alt.
PARAMETER
STK12C68-25
MIN MAX
1
tELQV
2
tAVAVg
3
tAVQVh
4
tGLQV
5
tAXQXh
6
tELQX
7
tEHQZi
8
tGLQX
9
tGHQZi
10
tELICCHf
11
tEHICCLf
tACS
tRC
tAA
tOE
tOH
tLZ
tHZ
tOLZ
tOHZ
tPA
tPS
Chip Enable Access Time
Read Cycle Time
Address Access Time
Output Enable to Data Valid
Output Hold after Address Change
Chip Enable to Output Active
Chip Disable to Output Inactive
Output Enable to Output Active
Output Disable to Output Inactive
Chip Enable to Power Active
Chip Disable to Power Standby
25
25
25
10
5
5
10
0
10
0
25
Note g: W and HSB must be high during SRAM READ cycles.
Note h: Device is continuously selected with E and G both low.
Note i: Measured ± 200mV from steady state output voltage.
SRAM READ CYCLE #1: Address Controlledg, h
STK12C68-35
MIN MAX
35
35
35
15
5
5
10
0
10
0
35
(VCC = 5.0V ± 10%)e
STK12C68-45
MIN MAX
STK12C68-55
UNITS
MIN MAX
45
55
ns
45
55
ns
45
55
ns
20
35
ns
5
5
ns
5
5
ns
12
12
ns
0
0
ns
12
12
ns
0
0
ns
45
55
ns
ADDRESS
DQ (DATA OUT)
5
tAXQX
2
tAVAV
3
tAVQV
DATA VALID
SRAM READ CYCLE #2: E Controlledg
ADDRESS
E
6
tELQX
2
tAVAV
1
tELQV
G
DQ (DATA OUT)
ICC
4
8
tGLQV
tGLQX
10
tELICCH
STANDBY
ACTIVE
11
tEHICCL
7
tEHQZ
9
tGHQZ
DATA VALID
October 2003
3 Document Control # ML0008 rev 0.4
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