MSM82C54-2RS 查看數據表（PDF） - Oki Electric Industry
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MSM82C54-2RS Datasheet PDF : 23 Pages
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¡ Semiconductor
MSM82C54-2RS/GS/JS
DESCRIPTION OF BASIC OPERATIONS
Data transfers between the internal registers and external data bus is outlined in the following
table.
CS RD WR A1 A0
Function
0
1
0
0
0
Data Bus to Counter #0 Writing
0
1
0
0
1
Data Bus to Counter #1 Writing
0
1
0
1
0
Data Bus to Counter #2 Writing
0
1
0
1
1
Data Bus to Control Word Register Writing
0
0
1
0
0
Data Bus from Counter #0 Writing
0
0
1
0
1
Data Bus from Counter #1 Writing
0
0
1
1
0
Data Bus from Counter #2 Writing
0
0
1
1
1
1
¥
¥
¥
¥
Data Bus in High Impedance Status
0
1
1
¥
¥
¥: denotes "not specified"
DESCRIPTION OF OPERATION
MSM82C54-2 functions are selected by control words from the CPU. In the required program
sequence, the control word setting is followed by the count value setting and execution of the
desired timer operation.
Control Word and Count Value Program
Each counter operating mode is set by control word programming. The control word format
is outlined below.
D7
D6
D5
D4
D3
D2
D1
D0
SC1
SC0
RL1
RL0
M2
M1
M0
BCD
Select Counter
Read/Load
Mode
BCD
(CS=0, A0, A1=1, 1, RD=1, WR=0)
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