IDT72132 查看數據表（PDF） - Integrated Device Technology

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IDT72132

CMOS SERIAL-TO-PARALLEL FIFO 2048 x 9 4096 x 9

Integrated Device Technology 

IDT72132, IDT72142

CMOS SERIAL-TO-PARALLEL FIFO 2048 x 9 AND 4096 x 9

AC TEST CONDITIONS

Input Pulse Levels

Input Rise/Fall Times

Input Timing Reference Levels

Output Reference Levels

Output Load

GND to 3.0V

5ns

1.5V

1.5V

See Figure A

2752 tbl 08

COMMERCIAL TEMPERATURE RANGES

5V

D.U.T.

680Ω

1.1K

Ω

30pF*

FUNCTIONAL DESCRIPTION

2752 drw 03

or equivalent circuit

Figure A. Output Load

*Includies jig and scope capacitances

Serial Data Input

The serial data is input on the SI pin. The data is clocked

in on the rising edge of SICP providing the Full Flag (FF) is not

asserted. If the Full Flag is asserted then the next parallel data

word is inhibited from moving into the RAM array. NOTE:

SICP should not be clocked once the last bit of the last word

has been shifted in, as indicated by NW HIGH and FF LOW.

If it is, then the input data will be lost.

The serial word is shifted in Least Significant Bit first. Thus,

when the FIFO is read, the Least Significant Bit will come out

on Q0 and the second bit is on Q1 and so on. The serial word

width must be programmed by connecting the appropriate

Data Set line (D7, D8) to the NW input. The data set lines are

taps off a digital delay line. Selecting one of these taps

programs the width of the serial word to be written in.

Parallel Data Output

A read cycle is initiated on the falling edge of Read (R)

provided the Empty Flag is not set. The output data is

accessed on a first-in/first-out basis, independent of the

ongoing write operations. The data is available tA after the

falling edge of R and the output bus Q goes into high imped-

ance after R goes HIGH.

Alternately, the user can access the FIFO by keeping R

LOW and enabling data on the bus by asserting Output Enable

(OE). When R is LOW, the OE signal enables data on the

output bus. When R is LOW and OE is HIGH, the output bus

is three-stated. When R is HIGH, the output bus is disabled

irrespective of OE.

RS

SICP

R

AEF, EF

HF, FF

D7 ,D8

t RSDL

t RSC

t RS

t RSS

tRSS

tRSF1

tRSF2

tRSR

0

n-1

(1)

t PDI

NOTE:

1. Input bits are numbered 0 to n-1. D7 and D8 correspond to n=8 and n=9 respectively

Figure 1. Reset

2752 drw 04

5.36

5

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