AD7722AS(Rev0) 查看數據表（PDF） - Analog Devices
零件编号
产品描述 (功能)
生产厂家
AD7722AS Datasheet PDF : 24 Pages
| |||
AD7722
TIMING SPECIFICATIONS (AVDD= +5 V ؎ 5%, DVDD = +5 V ؎ 5%, AGND = DGND = 0 V, CL = 50 pF, TA = TMIN to TMAX,
fCLKIN = 12.5 MHz, SFMT = Logic Low or High, CFMT = Logic Low or High)
Symbol Min
Typ
Max
CLKIN Frequency
fCLK
CLKIN Period (tCLK = 1/fCLK)
t1
CLKIN Low Pulse Width
t2
CLKIN High Pulse Width
t3
CLKIN Rise Time
t4
CLKIN Fall Time
t5
FSI Low Time
t6
FSI Setup Time
t7
FSI Hold Time
t8
CLKIN to SCO Delay
t9
SCO Period1
t10
SCO Transition to FSO High Delay
t11
SCO Transition to FSO Low Delay
t12
SCO Transition to SDO Valid Delay
t13
SCO Transition from FSI2
t14
SDO Enable Delay Time
t15
SDO Disable Delay Time
t16
DRDY High Time
t17
Conversion Time1
t18
DRDY to CS Setup Time
t19
CS to RD Setup Time
t20
RD Pulse Width
t21
Data Access Time after RD Falling Edge3
t22
Bus Relinquish Time after RD Rising Edge
t23
CS to RD Hold Time
t24
RD to DRDY High Time
t25
SYNC/RESET Input Pulse Width
t26
DVAL Low Delay from SYNC/RESET
t27
SYNC/RESET Low Time Before CLKIN Rising t28
DRDY High Delay after SYNC/RESET Low
t29
DRDY Low Delay after SYNC/RESET Low1
t30
DVAL High Delay after SYNC/RESET Low1
t31
CAL Setup Time
t34
CAL Pulse Width
t35
Calibration Delay from CAL High
t36
Unipolar Input Calibration Time, (UNI = “0”)1 t37
Bipolar Input Calibration Time, (UNI = “1”)1 t37
Conversion Results Valid, (UNI = “0”)1
t38
Conversion Results Valid, (UNI = “1”)1
t38
NOTES
1Guaranteed by design.
2Frame Sync is initiated on falling edge of CLKIN.
3With RD synchronous to CLKIN t22, can be reduced up to 1 tCLK.
0.3
12.5
0.067
0.08
0.45 × t1
0.45 × t1
5
5
2
20
20
40
2
4
4
3
30
10
2
64
0
0
tCLK + 20
0
1
10
10
10
1
15
3.33
0.55 × t1
0.55 × t1
10
10
8
2.5
45
30
tCLK + 40
tCLK + 40
40
50
(8192 + 64)
8192
2
64
(3 × 8192 + 2 × 512)
(4 × 8192 + 3 × 512)
(3 × 8192 + 2 × 512 + 64)
(4 × 8192 + 3 × 512 + 64)
Units
MHz
µs
ns
ns
tCLK
ns
ns
ns
tCLK
ns
ns
ns
tCLK
ns
ns
tCLK
tCLK
ns
ns
ns
ns
ns
ns
tCLK
ns
ns
ns
ns
tCLK
tCLK
ns
tCLK
tCLK
tCLK
tCLK
tCLK
tCLK
–4–
REV. 0
Share Link: 