AD7722AS(Rev0) 查看數據表（PDF） - Analog Devices
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AD7722AS Datasheet PDF : 24 Pages
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AD7722
PIN CONFIGURATION
44-Pin PQFP (S-44)
44 43 42 41 40 39 38 37 36 35 34
DGND/DB2 1
DGND/DB1 2
DGND/DB0 3
CFMT/DRDY 4
DVAL/RD 5
DGND 6
UNI 7
P/S 8
AGND 9
AGND1 10
CLKIN 11
PIN 1
IDENTIFIER
AD7722
TOP VIEW
(Not to Scale)
33 DGND/DB13
32 DGND/DB14
31 DGND/DB15
30 SYNC
29 CS
28 DGND
27 CAL
26 AGND
25 AGND
24 REF2
23 AVDD
12 13 14 15 16 17 18 19 20 21 22
Mnemonic
DVAL/RD
CFMT/DRDY
DGND/DB15
DGND/DB14
DGND/DB13
DGND/DB12
DGND/DB11
DGND/DB10
FSO/DB9
SDO/DB8
SCO/DB7
FSI/DB6
SFMT/DB5
DOE/DB4
TSI/DB3
DGND/DB2
DGND/DB1
DGND/DB0
PARALLEL MODE PIN FUNCTION DESCRIPTION
Pin No. Description
5
Read Input is a level sensitive logic input. The RD logic level is sensed on the rising edge of CLKIN.
This digital input can be used in conjunction with CS to read data from the device. The output data
bus is enabled when the rising edge of CLKIN senses a logic low level on RD if CS is also low. When
RD is sensed high, the output data bits DB15–DB0 will be high impedance.
2
Data Ready Logic Output. A falling edge indicates a new output word is available to be read from out-
put data register. DRDY will return high upon completion of a read operation. If a read operation
does not occur between output updates, DRDY will pulse high for two CLKIN cycles before the next
output update. DRDY also indicates when conversion results are available after a SYNC or RESET
sequence and when completing a self-calibration.
31
Data Output Bit (MSB)
32
Data Output Bit
33
Data Output Bit
34
Data Output Bit
35
Data Output Bit
36
Data Output Bit
37
Data Output Bit
38
Data Output Bit
40
Data Output Bit
41
Data Output Bit
42
Data Output Bit
43
Data Output Bit
44
Data Output Bit
1
Data Output Bit
2
Data Output Bit
3
Data Output Bit (LSB)
–8–
REV. 0
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