AD7713(RevC) 查看數據表（PDF） - Analog Devices
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AD7713 Datasheet PDF : 28 Pages
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AD7713–SPECIFICATIONS
Parameter
A, S Versions1
Units
Conditions/Comments
POWER REQUIREMENTS
Power Supply Voltages
AVDD Voltage
DVDD Voltage16
Power Supply Currents
AVDD Current
DVDD Current
Power Supply Rejection17
(AVDD and DVDD)
Power Dissipation
Normal Mode
Standby (Power-Down) Mode
+5 to +10
+5
0.6
0.7
0.5
1
See Note 18
5.5
300
V nom
V nom
± 5% for Specified Performance
± 5% for Specified Performance
mA max
mA max
mA max
mA max
dB typ
AVDD = +5 V
AVDD = +10 V
fCLK IN = 1 MHz. Digital Inputs 0 V to DVDD
fCLK IN = 2 MHz. Digital Inputs 0 V to DVDD
Rejection w.r.t. AGND
mW max
µW max
AVDD = DVDD = +5 V, fCLK IN = 1 MHz; Typically 3.5 mW
AVDD = DVDD = +5 V, Typically 150 µW
NOTES
16The ± 5% tolerance on the DVDD input is allowed provided that DVDD does not exceed AVDD by more than 0.3 V.
17Measured at dc and applies in the selected passband. PSRR at 50 Hz will exceed 120 dB with filter notches of 2 Hz, 5 Hz, 10 Hz, 25 Hz or 50 Hz. PSRR at 60 Hz
will exceed 120 dB with filter notches of 2 Hz, 6 Hz, 10 Hz, 30 Hz or 60 Hz.
18PSRR depends on gain: gain of 1 = 70 dB typ; gain of 2 = 75 dB typ; gain of 4 = 80 dB typ; gains of 8 to 128 = 85 dB typ.
Specifications subject to change without notice.
TIMING CHARACTERISTICS1, 2 (DVDD = +5 V ± 5%; AVDD = +5 V or +10 V ± 5%; AGND = DGND = 0 V; fCLKIN =2 MHz;
Input Logic 0 = 0 V, Logic 1 = DVDD unless otherwise noted.)
Parameter
Limit at TMIN, TMAX
(A, S Versions)
Units
Conditions/Comments
fCLK
3,
IN
4
tCLK IN LO
tCLK IN HI
tr5
tf5
t1
Self-Clocking Mode
t2
t3
t4
t5
t6
t76
t86
t9
t10
t14
t15
t16
t17
t18
t19
400
2
0.4 × tCLK IN
0.4 × tCLK IN
50
50
1000
0
0
2 × tCLK IN
0
4 × tCLK IN + 20
4 × tCLK IN +20
tCLK IN/2
tCLK IN/2 + 30
tCLK IN/2
3 × tCLK IN/2
50
0
4 × tCLK IN + 20
4 × tCLK IN
0
10
kHz min
MHz max
ns min
ns min
ns max
ns max
ns min
ns min
ns min
ns min
ns min
ns max
ns max
ns min
ns max
ns nom
ns nom
ns min
ns min
ns max
ns min
ns min
ns min
Master Clock Frequency: Crystal Oscillator or
Externally Supplied for Specified Performance
Master Clock Input Low Time; tCLK IN = 1/fCLK IN
Master Clock Input High Time
Digital Output Rise Time; Typically 20 ns
Digital Output Fall Time; Typically 20 ns
SYNC Pulse Width
DRDY to RFS Setup Time
DRDY to RFS Hold Time
A0 to RFS Setup Time
A0 to RFS Hold Time
RFS Low to SCLK Falling Edge
Data Access Time (RFS Low to Data Valid)
SCLK Falling Edge to Data Valid Delay
SCLK High Pulse Width
SCLK Low Pulse Width
A0 to TFS Setup Time
A0 to TFS Hold Time
TFS to SCLK Falling Edge Delay Time
TFS to SCLK Falling Edge Hold Time
Data Valid to SCLK Setup Time
Data Valid to SCLK Hold Time
–4–
REV. C
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