CXL1502M 查看數據表（PDF） - Sony Semiconductor

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CXL1502M

CMOS-CCD Signal Processor

Sony Semiconductor 

CXL1502M

Notes)

∗1 Adjust the output amplitude of the inversion and the non-inversion amplifiers in the signal input block to an

equal value, as well as the phase difference to a precise 180°.

Also set the clock and input signal frequency accurately.

∗2 VIC, VIY, VID and VIT are defined as follows:

VIC, VIY, VID and VIT are input signal clamp levels. They clamps the Video signal sync tip level. They are

the pin voltages at no-input signal for pins 3, 2, 30 and 5, respectively.

Input (CCD3)

Input (CCDY)

Input (CCD2-C)

VID

30

23

L1502

5

VIY

VIT

VIC

Input (CCD1)

Testing of VIC, VIY, VID and VIT is executed with a voltmeter under the following SW conditions:

Item

SW conditions

Test

1 2 3 4 5 6 7 8 9 10 11 point

VIC — b b b b a a a a — — V3

VIY — b b b b a a a a — — V2

VID — b b b b a a a a — — V1

VIT — b b b b a a a a — — V4

∗3 This is the IC supply current value during clock and signal input.

∗4 GLC, GLY, GLD and GLT are output gains of C-CD, Y-YD, YD and TH pins when a 500mVp-p,

203.126kHz sine wave is simultaneously fed to CCD2-C, CCDY, CCD3 and CCD1 pins, respectively.

(Example of calculation)

GLC = 20 log C-CD pin output voltage [mVp-p] [dB]

500 [mVp-p]

–7–

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