AT80C51RA2-3CSCV 查看數據表（PDF） - Atmel Corporation

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AT80C51RA2-3CSCV

High Performance 8-bit Microcontrollers

Atmel Corporation 

AT/TS8xC51Rx2

6.1 Expanded RAM (XRAM)

The TS80C51Rx2 provide additional Bytes of ramdom access memory (RAM) space for

increased data parameter handling and high level language usage.

RA2, RB2 and RC2 devices have 256 bytes of expanded RAM, from 00H to FFH in external

data space; RD2 devices have 768 bytes of expanded RAM, from 00H to 2FFH in external data

space.

The TS80C51Rx2 has internal data memory that is mapped into four separate segments.

The four segments are:

• 1. The Lower 128 bytes of RAM (addresses 00H to 7FH) are directly and indirectly

addressable.

• 2. The Upper 128 bytes of RAM (addresses 80H to FFH) are indirectly addressable only.

• 3. The Special Function Registers, SFRs, (addresses 80H to FFH) are directly addressable

only.

• 4. The expanded RAM bytes are indirectly accessed by MOVX instructions, and with the

EXTRAM bit cleared in the AUXR register. (See Table 6-1.)

The Lower 128 bytes can be accessed by either direct or indirect addressing. The Upper 128

bytes can be accessed by indirect addressing only. The Upper 128 bytes occupy the same

address space as the SFR. That means they have the same address, but are physically sepa-

rate from SFR space.

When an instruction accesses an internal location above address 7FH, the CPU knows whether

the access is to the upper 128 bytes of data RAM or to SFR space by the addressing mode used

in the instruction.

• Instructions that use direct addressing access SFR space. For example: MOV 0A0H, #

data, accesses the SFR at location 0A0H (which is P2).

• Instructions that use indirect addressing access the Upper 128 bytes of data RAM. For

example: MOV @R0, # data where R0 contains 0A0H, accesses the data byte at address

0A0H, rather than P2 (whose address is 0A0H).

• The 256 or 768 XRAM bytes can be accessed by indirect addressing, with EXTRAM bit

cleared and MOVX instructions. This part of memory which is physically located on-chip,

logically occupies the first 256 or 768 bytes of external data memory.

• With EXTRAM = 0, the XRAM is indirectly addressed, using the MOVX instruction in

combination with any of the registers R0, R1 of the selected bank or DPTR. An access to

XRAM will not affect ports P0, P2, P3.6 (WR) and P3.7 (RD). For example, with EXTRAM

= 0, MOVX @R0, # data where R0 contains 0A0H, accesses the XRAM at address 0A0H

rather than external memory. An access to external data memory locations higher than FFH

(i.e. 0100H to FFFFH) (higher than 2FFH (i.e. 0300H to FFFFH for RD devices) will be

performed with the MOVX DPTR instructions in the same way as in the standard 80C51, so

with P0 and P2 as data/address busses, and P3.6 and P3.7 as write and read timing signals.

Refer to Figure 6-1. For RD devices, accesses to expanded RAM from 100H to 2FFH can

only be done thanks to the use of DPTR.

• With EXTRAM = 1, MOVX @Ri and MOVX @DPTR will be similar to the standard 80C51.

MOVX @ Ri will provide an eight-bit address multiplexed with data on Port0 and any output

port pins can be used to output higher order address bits. This is to provide the external

paging capability. MOVX @DPTR will generate a sixteen-bit address. Port2 outputs the high-

order eight address bits (the contents of DPH) while Port0 multiplexes the low-order eight

17

4188F–8051–01/08

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