AT80C51RA2-3CSCV 查看數據表（PDF） - Atmel Corporation

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AT80C51RA2-3CSCV

High Performance 8-bit Microcontrollers

Atmel Corporation 

address bits (DPL) with data. MOVX @ Ri and MOVX @DPTR will generate either read or

write signals on P3.6 (WR) and P3.7 (RD).

The stack pointer (SP) may be located anywhere in the 256 bytes RAM (lower and upper RAM)

internal data memory. The stack may not be located in the XRAM.

Figure 6-1. Internal and External Data Memory Address

FF(RA, RB, RC)/2FF (RD)

FF

FF

FFFF

XRAM

256 bytes

Upper

128 bytes

Internal

Ram

indirect accesses

80

Special

Function

Register

direct accesses

80

External

Data

Memory

Lower

128 bytes

Internal

Ram

direct or indirect

accesses

0100 (RA, RB, RC) or 0300 (RD)

00

00

0000

Table 6-1. Auxiliary Register AUXR

AUXR

Address 08EH

-

-

-

-

-

-

EXTRAM AO

Reset value

X

X

X

X

X

X

0

0

Symbol

Function

-

Not implemented, reserved for future use. (1)

AO

Disable/Enable ALE

AO

Operating Mode

0

ALE is emitted at a constant rate of 1/6 the oscillator frequency (or 1/3 if X2 mode

is used)

1

ALE is active only during a MOVX or MOVC instruction

EXTRAM Internal/External RAM (00H-FFH) access using MOVX @ Ri/ @ DPTR

EXTRAM Operating Mode

0

Internal XRAM access using MOVX @ Ri/ @ DPTR

1

External data memory access

1.

User software should not write 1s to reserved bits. These bits may be used in future 8051 family

products to invoke new features. In that case, the reset or inactive value of the new bit will be 0,

and its active value will be 1. The value read from a reserved bit is indeterminate.

18 AT/TS8xC51Rx2

4188F–8051–01/08

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