AD9805 查看數據表（PDF） - Analog Devices

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AD9805

Complete 12-Bit/10-Bit 6 MSPS CCD/CIS Signal Processors

Analog Devices 

AD9807/AD9805

Calculating Overall Gain

The overall gain for the AD9807/AD9805 can accommodate a

wide range of input voltage spans. The total gain is a composite

of analog gain (from the PGAs), digital gain (from the digital

multiplier) and the input span setting for the A/D (2 V or 4 V). To

determine the overall gain setting for the AD9807/AD9805, always

multiply the PGA gain setting by the digital gain setting. In

addition, the 2 V/4 V reference option can effectively provide

analog gain for input signals less than 2 V p-p.

Overall Gain = Analog Gain × Digital Gain

For example, with the PGA gain equal to 1 (gain setting equals

all “zeros”) and the digital multiplier equal to 1, the minimum

gain equals 1. With these settings, input signals can be as large

as 2 V or 4 V depending on the reference setting. Alternatively,

with the PGA gain equal to 4 (gain setting equals all “ones”)

and the digital multiplier equal to 8, the maximum gain equals

32. With the A/D reference span set to 2 V, an input signal span

as small as 62.5 mV p-p will produce a digital output spanning

from all “zeros” to all “ones.” For ranges between 62.5 mV and

4 V, see the Digital Gain and Analog Gain sections of the data

sheet.

Analog Gain

The transfer function of the PGA is:

Analog Input =

4

1

+

3

×

15 −

 15

x





where x is the decimal representation of the settings in the PGA

gain register. Figure 16 shows the graph of this transfer

function on both a linear and logarithmic scale. The transfer

function is approximately linear in dB.

4.0

12

3.5

10

3.0

8

where GAIN<n:0> is the decimal representation of the GAIN

bus data bits, Y = 4096 for the AD9807, Y = 1024 for the

AD9805, and X equals 1, 3 or 7 depending on Bits 0–2 in the

Configuration Register.

Overall Transfer Function

The overall transfer function for the AD9807 can be calculated

as follows:

[ ] ( ) V IN ± InputOffset × PGA Gain

ADC OUT =

2 ×V REF

× 4096

DOUT = [ADCOUT + Offset Register – Offset Bus][Digital Gain]

Choosing the Input Coupling Capacitors

Because of the dc offset present at the output of CCDs, it is likely

that these outputs will require some form of dc restoration to be

compatible with the input requirements of the AD9807/AD9805.

To simplify input level shifting, a dc blocking capacitor may be

used in conjunction with the internal biasing circuits of the

AD9807/AD9805 to accomplish the necessary dc restoration.

Figure 17 shows the equivalent analog input for the VINR,

VING and VINB inputs.

C

V IN

CDSCLK1

STRTLN

CDSCLK2

AD9807/AD9805

IBIAS

S1

CONFIG

REG 2<7>

CONFIG

REG 2<0>

5kΩ

VBIAS

CONFIG

REG 2<6>

4pF

CDS

4pF

2.5

GAIN (dB)

6

2.0

4

GAIN

1.5

2

1.0

0

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

PGA GAIN SETTING

Figure 16. PGA Transfer Function

Digital Gain

The digital multiplier section of the AD9807/AD9805 allows the

user to apply gain in addition to that afforded by the analog

PGA. The minimum gain of the digital multiplier is always 1.

The user sets the maximum gain of the digital multiplier to be 8,

4, or 2 with Bits 0–2 in the Configuration Register. (The max

gain is the same for all three channels.) The digital gain

applied to the output from the digital subtracter is calculated

using the equation:

Digital

Gain

=



1



+

Gain <



Y

n:0

>



×

X







Figure 17. Equivalent Analog Inputs (VINR, VING, and

VINB)

Enabling CDS functionality and Line Clamp Mode with Bits 0,

6 and 7 in Configuration Register 2 allows switch S1 to turn on

when STRTLN is low and CDSCLK1 goes high. This connects

a 5 kΩ biasing resistor to the inputs. This arrangement acts to

bias the average level of the input signal at voltage, VBIAS. The

voltage, VBIAS, changes depending on the selected PGA gain set-

ting. Specifically, for gain settings from 0 to 5, VBIAS equals 4 V;

for gain settings from 10 to 15, VBIAS equals 3 V. For gain set-

tings between 5 and 10, VBIAS decreases linearly from 4 V to 3 V.

The size of the coupling capacitor is dependent on several

factors including signal swing, allowable droop, and acquisition

time. The following procedure shows how to determine the

recommended range of capacitors.

Calculating CMAX

The maximum capacitor value is largely dependent on the

degree of accuracy and how quickly the input signal must be

level-shifted into the valid input range of the degree of accuracy.

Other factors affecting the speed of the capacitor charging or

REV. 0

–17–

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