AD9822JRS 查看數據表（PDF） - Analog Devices
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AD9822JRS Datasheet PDF : 20 Pages
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AD9822
SPECIFICATIONS
ANALOG SPECIFICATIONS
TMIN to TMAX, AVDD = 5 V, DRVDD = 5 V, CDS mode, fADCCLK = 15 MHz, fCDSCLK1 = fCDSCLK2 = 5 MHz, PGA gain = 1, unless otherwise noted.
Table 1.
Parameter
MAXIMUM CONVERSION RATE
3-Channel Mode with CDS
1-Channel Mode with CDS
ACCURACY (ENTIRE SIGNAL PATH)
ADC Resolution
Integral Nonlinearity (INL)
INL @ 6 MHz
Differential Nonlinearity (DNL)
DNL @ 6 MHz
No Missing Codes
No Missing Codes @ 6 MHz
Offset Error
Gain Error
ANALOG INPUTS
Input Signal Range1
Allowable Reset Transient1
Input Limits2
Input Capacitance
Input Bias Current
AMPLIFIERS
PGA Gain at Minimum
PGA Gain at Maximum
PGA Gain Resolution2
PGA Gain Monotonicity
Programmable Offset at Minimum
Programmable Offset at Maximum
Programmable Offset Resolution
Programmable Offset Monotonicity
NOISE AND CROSSTALK
Total Output Noise @ PGA Minimum
Total Output Noise @ PGA Maximum
Channel-to-Channel Crosstalk @ 6 MHz
POWER SUPPLY REJECTION
AVDD = 5 V ± 0.25 V
DIFFERENTIAL VREF (@ 25°C)
CAPT to CAPB (2 V ADC Full-Scale Range)
TEMPERATURE RANGE
Operating
Storage
POWER SUPPLIES
AVDD
DRVDD
OPERATING CURRENT
AVDD
DRVDD
Power-Down Mode Current
Min
15
12.5
−1.0
14
−240
−1.4
AVSS − 0.3
0.94
0
−65
4.75
3.0
Typ
14
−17.0/+3.5
−10.5/+1.5
−0.65/+0.75
−0.6/+0.65
14
−19
+3.5
2.0
1.0
10
10
1
5.7
64
Guaranteed
−350
+350
512
Guaranteed
1.5
6.0
<1
0.063
1.0
5.0
5.0
73
4
150
Max
+1.1
+200
+6.9
AVDD + 0.3
0.9
1.06
+70
+150
5.25
5.25
Unit
MSPS
MSPS
Bits
LSB
LSB
LSB
LSB
Bits
Bits
mV
% FSR
V p-p
V
V
pF
nA
V/V
V/V
Steps
mV
mV
Steps
LSB rms
LSB rms
LSB
% FSR
V
°C
°C
V
V
mA
mA
µA
Rev. B | Page 3 of 20
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