AD9822JRSZ 查看數據表（PDF） - Analog Devices
零件编号
产品描述 (功能)
生产厂家
AD9822JRSZ Datasheet PDF : 20 Pages
| |||
TIMING SPECIFICATIONS
TMIN to TMAX, AVDD = 5 V, DRVDD = 5 V.
Table 3.
Parameter
CLOCK PARAMETERS
3-Channel Pixel Rate
1-Channel Pixel Rate
ADCCLK Pulse Width
CDSCLK1 Pulse Width
CDSCLK2 Pulse Width
CDSCLK1 Falling to CDSCLK2 Rising
ADCCLK Falling to CDSCLK2 Rising
CDSCLK2 Rising to ADCCLK Rising
CDSCLK2 Falling to ADCCLK Falling
CDSCLK2 Falling to CDSCLK1 Rising
ADCCLK Falling to CDSCLK1 Rising
Aperture Delay for CDS Clocks
SERIAL INTERFACE
Maximum SCLK Frequency
SLOAD to SCLK Setup Time
SCLK to SLOAD Hold Time
SDATA to SCLK Rising Setup Time
SCLK Rising to SDATA Hold Time
SCLK Falling to SDATA Valid
DATA OUTPUT
Output Delay
Three-State to Data Valid
Output Enable High to Three-State
Latency (Pipeline Delay)
AD9822
Symbol
tPRA
tPRB
tADCLK
tC1
tC2
tC1C2
tADC2
tC2ADR
tC2ADF
tC2C1
tADC1
tAD
fSCLK
tLS
tLH
tDS
tDH
tRDV
tOD
tDV
tHZ
Min
Typ
67
80
30
10
10
0
0
0
30
40
30
40
0
2
10
10
10
10
10
10
8
10
10
3 (Fixed)
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
ns
ns
ns
ns
ns
ns
ns
ns
Cycles
Rev. B | Page 5 of 20
Share Link: 