LTC1401 查看數據表（PDF） - Linear Technology
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LTC1401 Datasheet PDF : 20 Pages
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LTC1401
WU
TI I G CHARACTERISTICS (Note 5)
SYMBOL
fSAMPLE(MAX)
tCONV
tACQ
fCLK
tCLK
tWK(NAP)
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
PARAMETER
Maximum Sampling Frequency
Conversion Time
Acquisition Time
CLK Frequency
CLK Pulse Width
Time to Wake Up from Nap Mode
CLK Pulse Width to Return to Active Mode
CONV↑ to CLK↑ Setup Time
CONV↑ After Leading CLK↑
CONV Pulse Width
Time from CLK↑ to Sample Mode
Aperture Delay of Sample-and-Hold
Minimum Delay Between Conversion
Delay Time, CLK↑ to DOUT Valid
Delay Time, CLK↑ to DOUT Hi-Z
Time from Previous Data Remains Valid After CLK↑
The q denotes specifications which apply over the full operating
temperature range; all other limits and typicals apply to TA = 25°C.
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: All voltage values are with respect to GND.
Note 3: When these pin voltages are taken below GND or above VCC, they
will be clamped by internal diodes. This product can handle input currents
greater than 40mA without latch-up if the pin is driven below GND or
above VCC.
Note 4: When these pin voltages are taken below GND, they will be clamped
by internal diodes. This product can handle input currents greater than 40mA
without latch-up if the pin is driven below GND. These pins are not clamped
to VCC.
CONDITIONS
fCLK = 3.2MHz
(Note 6)
(Note 8)
Jitter < 50ps
(Note 6)
CLOAD = 20pF
CLOAD = 20pF
CLOAD = 20pF
MIN TYP MAX UNITS
q 200
kHz
q
4.1
µs
315
ns
q 0.1
3.2
MHz
q 60
ns
350
ns
q 60
ns
q 100
ns
q0
ns
q 50
ns
80
ns
45
ns
q
350
550
ns
q
60
120
ns
q
60
120
ns
q 15
50
ns
Note 5: VCC = 3V, fSAMPLE = 200kHz, tr = tf = 5ns unless otherwise
specified.
Note 6: Guaranteed by design, not subject to test.
Note 7: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 8: The rising edge of CONV starts a conversion. If CONV returns low
at a bit decision point during the conversion, it can create small errors. For
best performance, ensure that CONV returns low either within 120ns after
the conversion starts (i.e., before the first bit decision) or after the 14
clock cycles. (Figure 13 Timing Diagram).
4
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