TX4939 查看數據表（PDF） - Toshiba
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TX4939 Datasheet PDF : 756 Pages
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Index
Toshiba RISC Processor
TX4939
17.5.5. Issuing Timing of Reset Signal................................................................................................................. 17-34
17.5.6. Command Packet Transmission Timing ................................................................................................... 17-35
17.6. Basic Operation Setup .................................................................................................................................... 17-36
17.7. ATA Bus Access Timing (ATA/ATAPI-6 Spec. Values)...................................................................................... 17-37
17.7.1. PIO Mode................................................................................................................................................. 17-37
17.7.2. Multiword DMA Mode ............................................................................................................................... 17-37
CHAPTER 18. DUAL ETHERNET MAC CONTROLLER.............................................................................................. 18-1
18.1. Features............................................................................................................................................................ 18-1
18.2. Block diagram ................................................................................................................................................... 18-2
18.3. Detailed explanation.......................................................................................................................................... 18-4
18.3.1. Accessing the Ethernet Controller.............................................................................................................. 18-4
18.3.2. Data structure............................................................................................................................................. 18-7
18.3.3. System control model................................................................................................................................. 18-9
18.3.4. Functional overview ................................................................................................................................. 18-10
18.3.5. DMA function block .................................................................................................................................. 18-13
18.3.6. MAC function blocks ................................................................................................................................ 18-13
18.3.7. Memory configuration............................................................................................................................... 18-15
18.3.8. MAC operation ......................................................................................................................................... 18-20
18.3.9. DMA operation ......................................................................................................................................... 18-31
18.4. Registers......................................................................................................................................................... 18-35
18.4.1. Overview .................................................................................................................................................. 18-35
18.4.2. PCI Configuration Register group ............................................................................................................ 18-38
18.4.3. DMA Control, Status Register group ........................................................................................................ 18-47
18.4.4. Flow Control Register group .................................................................................................................... 18-59
18.4.5. MAC Control, Status Register group ........................................................................................................ 18-61
CHAPTER 19. QUAD SIO ............................................................................................................................................. 19-1
19.1. Features............................................................................................................................................................ 19-1
19.2. Block Diagram................................................................................................................................................... 19-2
19.3. Detailed Explanation ......................................................................................................................................... 19-3
19.3.1. Overview .................................................................................................................................................... 19-3
19.3.2. Data Format ............................................................................................................................................... 19-3
19.3.3. Serial Clock Generator............................................................................................................................... 19-5
19.3.4. Data Reception .......................................................................................................................................... 19-7
19.3.5. Data Transmission...................................................................................................................................... 19-7
19.3.6. DMA Transfer ............................................................................................................................................. 19-8
19.3.7. Flow Control............................................................................................................................................... 19-8
19.3.8. Reception Data Status ............................................................................................................................... 19-8
19.3.9. Reception Time Out ................................................................................................................................... 19-9
19.3.10. Software Reset......................................................................................................................................... 19-9
19.3.11. Error Detection/Interrupt Signaling ......................................................................................................... 19-10
19.3.12. Multi-Controller System...........................................................................................................................19-11
19.4. Registers......................................................................................................................................................... 19-12
19.4.1. Line Control Register 0,1,2,3 ................................................................................................................... 19-13
19.4.2. DMA/Interrupt Control Register 0,1,2,3 .................................................................................................... 19-15
19.4.3. DMA/Interrupt Status Register 0,1,2,3...................................................................................................... 19-17
19.4.4. Status Change Interrupt Status Register 0,1,2,3 ...................................................................................... 19-19
19.4.5. FIFO Control Register 0,1,2,3 .................................................................................................................. 19-20
19.4.6. Flow Control Register 0,1,2,3................................................................................................................... 19-21
19.4.7. Baud Rate Control Register 0,1,2,3 ......................................................................................................... 19-23
19.4.8. Transmit FIFO Register 0,1,2,3 ................................................................................................................ 19-24
19.4.9. Receive FIFO Register 0,1,2,3................................................................................................................. 19-25
CHAPTER 20. SPI INTERFACE.................................................................................................................................... 20-1
20.1. Features............................................................................................................................................................ 20-1
20.2. Block diagram ................................................................................................................................................... 20-2
20.3. Operational description ..................................................................................................................................... 20-3
20.3.1. Operation modes ....................................................................................................................................... 20-3
20.3.2. Transmitter/Receiver .................................................................................................................................. 20-3
20.3.3. Baud Rate Generator ................................................................................................................................. 20-4
20.3.4. Transfer format........................................................................................................................................... 20-5
20.3.5. Interframe Delay Time Counter .................................................................................................................. 20-6
20.3.6. Buffer configuration .................................................................................................................................... 20-7
20.3.7. SPI system errors....................................................................................................................................... 20-7
20.3.8. Interrupts.................................................................................................................................................... 20-7
Rev. 3.3 May 18, 2007
viii
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