TX4939 查看數據表（PDF） - Toshiba

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TX4939

64-Bit TX System RISC

Toshiba 

Toshiba RISC Processor

Index

TX4939

Figure 9-2 Normal Mode (ACEHOLD=0) ................................................................................................................ 9-6

Figure 9-3 External ACK Mode (ACEHOLD=0) ...................................................................................................... 9-6

Figure 9-4 Ready Mode (ACEHOLD=0) ................................................................................................................. 9-7

Figure 9-5 Page Mode (ACEHOLD=0) ................................................................................................................... 9-7

Figure 9-6 SWHT Disable (Normal Mode, Single Read/Write Cycle) ..................................................................... 9-8

Figure 9-7 SHWT 1 Wait (Normal Mode, Single Read/Write Cycle) ....................................................................... 9-9

Figure 9-8 ACK* Output Timing (Single Read/Write Cycle) .................................................................................. 9-10

Figure 9-9 ACK* Input Timing (Single Read/Write Cycle) ......................................................................................9-11

Figure 9-10 ACK* Input Timing (Burst Reade Cycle) ............................................................................................ 9-12

Figure 9-11 ACK* Input Timing (Burst Write Cycle)............................................................................................... 9-12

Figure 9-12 Ready Input Timing (Read Cycle)...................................................................................................... 9-13

Figure 9-13 Ready Input Timing (Write Cycle)...................................................................................................... 9-13

Figure 9-14 Physical Address Mapping of the ISA Spaces ................................................................................... 9-14

Figure 9-15 ACE* Signal (CCFG.ACEHOLD=1, PWT: WT=0, SHWT=0, Normal) ................................................ 9-19

Figure 9-16 ACE* Signal (CCFG.ACEHOLD=0, PWT: WT=0, SHWT=0, Normal) ................................................ 9-19

Figure 9-17 Double-word Single Write (PWT: WT=0, SHWT=0, Normal, 16-bit Bus) ........................................... 9-20

Figure 9-18 Double-word Single Read (PWT: WT=0, SHWT=0, Normal, 16-bit Bus)........................................... 9-20

Figure 9-19 Half-word Single Write/Read (PWT: WT=0, SHWT=0, Normal, 16-bit Bus) ...................................... 9-21

Figure 9-20 Half-word Single Read (PWT: WT=0, SHWT=0, Normal, 16-bit Bus)................................................ 9-21

Figure 9-21 4-word Burst Read (PWT: WT=0, SHWT=0, Normal, 16-bit Bus)...................................................... 9-22

Figure 9-22 4-word Burst Write (PWT: WT=0, SHWT=0, Normal, 16-bit Bus) ...................................................... 9-22

Figure 9-23 Double-word Single Write (PWT: WT=0, SHWT=0, Normal, 8-bit Bus) ............................................. 9-23

Figure 9-24 Double-word Single Read (PWT: WT=0, SHWT=0, Normal, 8-bit Bus)............................................. 9-23

Figure 9-25 1-byte Single Write / Read (PWT: WT=1, SHWT=0, Normal, 8-bit Bus) ............................................ 9-24

Figure 9-26 4-word Burst Write (PWT: WT=0, SHWT=0, Normal, 8-bit Bus) ........................................................ 9-25

Figure 9-27 4-word Burst Read (PWT: WT=0, SHWT=0, Normal, 8-bit Bus)........................................................ 9-25

Figure 9-28 4-word Burst Write (WT=1, PWT=0, SHWT=0, 4-page, 16-bit Bus) .................................................. 9-26

Figure 9-29 2-word Burst Read (WT=2, PWT=1, SHWT=0, 4-page, 16-bit Bus).................................................. 9-26

Figure 9-30 1-half-word Single Write (0 Wait, SHWT=0, External ACK*, 16-bit Bus) ........................................... 9-27

Figure 9-31 1-half-word Single Read (0 Wait, SHWT=0, External ACK*, 16-bit Bus) ........................................... 9-27

Figure 9-32 2-word Burst Write (0 Wait, SHWT=0, External ACK*, 16-bit Bus) .................................................... 9-28

Figure 9-33 2-word Burst Read (0 Wait, SHWT=0, External ACK*, 16-bit Bus).................................................... 9-29

Figure 9-34 Word Single Write (1 Wait, SHWT=2, External ACK*, 16-bit Bus) ..................................................... 9-30

Figure 9-35 Half-word Single Read (0 Wait, SHWT=2, External ACK*, 16-bit Bus).............................................. 9-30

Figure 9-36 Half-word Single Write (1 Wait, SHWT=2, External ACK*, 16-bit Bus) .............................................. 9-31

Figure 9-37 Half-word Single Read (0 Wait, SHWT=2, External ACK*, 16-bit Bus).............................................. 9-31

Figure 9-38 1-half-word Single Write (PWT: WT=2, SHWT=1, READY, 16-bit Bus) ............................................. 9-32

Figure 9-39 Half-word Single Read (PWT: WT=2, SHWT=1, READY, 16-bit Bus) ............................................... 9-32

Figure 9-40 ISA Half-Word Single Write (SHWT=2, READY, 16-bit Bus).............................................................. 9-33

Figure 9-41 ISA Half-Word Single Read (SHWT=2, READY, 16-bit Bus) ............................................................. 9-33

Figure 10-1 NAND Flash Memory Controller Block Diagram................................................................................ 10-2

Figure 10-2 Field Definition of Registers NDFDTR and NDFMCR ....................................................................... 10-3

Figure 10-3 Field Definition of Registers NDFDTR and NDFMCR ....................................................................... 10-5

Figure 10-4 ECC Position in NAND Data Space................................................................................................. 10-10

Figure 10-5 Byte Sequence of Little Endian and 8-bit bus...................................................................................10-11

Figure 10-6 Byte Sequence of Big Endian and 8-bit bus .....................................................................................10-11

Figure 10-7 Byte Sequence of Little Endian and 16-bit bus................................................................................ 10-12

Figure 10-8 Byte Sequence of Big Endian and 16-bit bus .................................................................................. 10-12

Figure 10-9 NAND Flash Memory Data Transfer Register (NDFDTR) ............................................................... 10-13

Figure 10-10 NAND Flash Memory Mode Control Register (NDFMCR)............................................................. 10-14

Figure 10-11 NAND Flash Memory Status Register (NDFSR)............................................................................ 10-15

Figure 10-12 NAND Flash Memory Interrupt Status Register (NDFISR) ............................................................ 10-15

Figure 10-13 NAND Flash Memory Interrupt Mask Register (NDFIMR) ............................................................. 10-16

Figure 10-14 NAND Flash Memory Strobe Pulse Width Register (NDFSPR)..................................................... 10-17

Figure 10-15 Initialization and Update Sequence ............................................................................................... 10-18

Figure 10-16 Command Cycles and Address Cycles and Read Cycle ............................................................... 10-19

Figure 10-17 Data Write Cycles.......................................................................................................................... 10-20

Figure 11-1 RTC Block Diagram ............................................................................................................................11-1

Figure 11-2 Port RTCCTL......................................................................................................................................11-5

Figure 11-3 Logic Diagram of Time Base Corrector...............................................................................................11-7

Figure 11-4 Definition of 8-BIT REGISTER............................................................................................................11-7

Figure 12-1 Block Diagram of Video Port Controller............................................................................................. 12-2

Figure 12-2 ITU.BT656 (CCIR656) Digital Video Timing ...................................................................................... 12-4

Figure 12-3 Transmission format with 188 Byte packets (VDVLD = 1) ................................................................. 12-4

Figure 12-4 Transmission format with 204 Byte packets ...................................................................................... 12-4

Figure 12-5 Transmission format with RS-coded packets (204 Bytes, VDVLD = 1) ............................................. 12-4

Rev. 3.3 May 18, 2007

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