U6813B-MFPG3 查看數據表（PDF） - Atmel Corporation
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U6813B-MFPG3 Datasheet PDF : 15 Pages
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U6813B
Table 1. Truth Table
VCC
3.3V
WDI
RELI
ok
ok
ok
H
ok
ok
ok
L (1)
ok
ok
ok
x
ok
ok
ok
x
ok
ok
wrong
x
x
wrong
x
x
wrong
x
x
x
Notes: 1. default state at open input
2. P-EN disable: low
3. N-EN disable: high
FETI
x
x
H
L (1)
x
x
x
RELO
on
off
x
x
off
off
off
FETO
x
x
on
off
off
off
off
N-RES
H
H
H
H
H
L
L
P-RES
L
L
L
L
L
H
H
P-EN (2)
H
H
H
H
L
L
L
N-EN (3)
L
L
L
L
H
H
H
Watchdog Description
Figure 3. Watchdog Block Diagram
WDC
Binary counter
Dual MUX
WDI
RESET
OSCERR
Slope
detector
Up/down
counter
RS-FF
WD-OK
WDI Input (Pin 11)
WDC Input (Pin 10)
4543A–AUTO–05/02
The microcontroller is monitored by a digital window watchdog which accepts an incom-
ming trigger signal of a constant frequency for correct operation. The frequency of the
trigger signal can be varied in a broad range as the watchdog’s time window is deter-
mined by external R/C components. The following description refers to the watchdog
timing diagram with tolerances (see Figure 4).
The microcontroller has to provide a trigger signal with the frequency fWDI which is fed to
the WDI input. A positive edge of fWDI detected by a slope detector resets the binary
counter and clocks the up/down counter.The latter one counts only from 0 to 3 or
reverse. Each correct trigger increments the up/down counter by 1, each wrong trigger
decrements it by 1. As soon as the counter reaches status 3, the RS flip-flop is set; see
Figure 5 (Watchdog state diagram). A missing incoming trigger signal is detected after
250 clocks of the internal watchdog frequency fRC (see WD_OK output) and resets the
up/down counter directly.
It is to be equiped by external R/C components. By means of an external R/C circuitry,
the IC generates a time base (frequency fWDC) independent from the microcontroller.
The watchdog’s time window refers to a frequency of fWDC = 100 ´ fWDI.
3
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