U6813B-MFPG3 查看數據表（PDF） - Atmel Corporation

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U6813B-MFPG3

Fail-safe IC with High-side and Relay Driver

Atmel Corporation 

Watchdog Window

Calculation

U6813B

Example with recommended values

Cosc = 6.8 nF (should be preferably 10%, NPO)

Rosc = 36 kW (can be 5%, Rosc < 200 kW due to leakage current and humidity)

RC oscillator

tWDC (s) = 10-3 [Cosc (nF) [(0.00078 Rosc (kW)) + 0.0005]]

fWDC (Hz) = 1 / (tWDC)

Watchdog WDI

fWDI (Hz) = 0.01 fWDC

tWDC = 200 µs ® fWDC = 5 kHz

fWDI = 50 Hz ® tWDI = 20 ms

WDI pulse width for fault detection after 3 pulses:

Upper watchdog window

Minimum: 169/ fWDC = 33.8 ms -> fWDC/ 169 = 29.55 Hz

Maximum: 170/ fWDC = 34 ms -> fWDC/ 170 = 29.4 Hz

Lower watchdog window

Minimum: 79/ fWDC = 15.8 ms -> fWDC / 79 = 63.3 Hz

Maximum: 80/ fWDC = 16 ms -> fWDC / 80 = 62.5 Hz

WDI dropouts for immediate fault detection:

Minimum: 250/ fWDC = 50.0 ms

Maximum: 251/ fWDC = 50.2 ms

Remarks to reset relay

The duration of the over- or undervoltage pulses determines the enable- and reset out-

puts. A pulse duration shorter than the debounce time has no effect on the outputs. A

pulse longer than the debounce time results in the first reset delay. If a pulse appears

during this delay, a second delay time is triggered. Therefore, the total reset delay time

can be longer than specified in the data sheet.

5

4543A–AUTO–05/02

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