UC62LS1008 查看數據表（PDF） - Unspecified

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UC62LS1008

Low Power CMOS SRAM 128K X 8 Bits

Unspecified 

Low Power CMOS SRAM

128K X 8 Bits

SWITCHING WAVEFORMS (READ CYCLE)

READ CYCLE1 (1,2,4)

ADDRESS

DOUT

tRC

tOH

tAA

UC62LS1008

-20/-25

tOH

READ CYCLE2 (1,3,4)

CE

DOUT

tCLZ(5)

tCE

READ CYCLE3 (1,4)

tCHZ(5)

tRC

ADDRESS

tAA

tOH

OE

CE

DOUT

tOLZ

tCLZ(5)

tOE

tCE

tOHZ(1,5)

tCHZ(5)

NOTES:

1. WE\ is high in read cycle.

2. Device is continuously selected when CE\ = VIL

3. Address valid prior to or coincident with CE\ transition low.

4. OE\ = VIL.

5. Transition is measured ±500mV from steady state with CL=5pF as shown in Figure 1B. The

parameter is guaranteed but not 100% tested.

U-Chip Technology Corp. LTD.

Reserves the right to modify document contents without notice.

Preliminary Rev. 1.0

PAGE 5

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