CS8900-IQ3 查看數據表（PDF） - Cirrus Logic

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CS8900-IQ3

Crystal LAN™ ISA Ethernet Controller

Cirrus Logic 

CS8900A

Crystal LAN™ ISA Ethernet Controller

TABLE OF CONTENTS

1.0 INTRODUCTION ......................................................................................................................7

1.1 General Description ............................................................................................................7

1.1.1 TDirect ISA-Bus Interface ......................................................................................7

1.1.2 TIntegrated Memory ..............................................................................................7

1.1.3 T802.3 Ethernet MAC Engine ................................................................................7

1.1.4 TEEPROM Interface ..............................................................................................7

1.1.5 TComplete Analog Front End ................................................................................7

1.2 System Applications ...........................................................................................................7

1.2.1 TMotherboard LANs ..............................................................................................7

1.2.2 TEthernet Adapter Cards .......................................................................................8

1.3 Key Features and Benefits .................................................................................................9

1.3.1 TVery Low Cost .....................................................................................................9

1.3.2 THigh Performance ................................................................................................9

1.3.3 TLow Power and Low Noise ..................................................................................9

1.3.4 TComplete Support ...............................................................................................9

2.0 PIN DESCRIPTION .............................................................................................................11

3.0 FUNCTIONAL DESCRIPTION ...............................................................................................16

3.1 Overview ..........................................................................................................................16

3.1.1 TConfiguration .....................................................................................................16

3.1.2 TPacket Transmission .........................................................................................16

3.1.3 TPacket Reception ..............................................................................................16

3.2 ISA Bus Interface .............................................................................................................17

3.2.1 TMemory Mode Operation ...................................................................................17

3.2.2 TI/O Mode Operation ...........................................................................................17

3.2.3 TInterrupt Request Signals ..................................................................................17

3.2.4 TDMA Signals ......................................................................................................17

3.3 Reset and Initialization .....................................................................................................18

3.3.1 TReset .................................................................................................................18

3.3.1.1 External Reset, or ISA Reset ...............................................................18

3.3.1.2 Power-Up Reset ..................................................................................18

3.3.1.3 Power-Down Reset ..............................................................................18

3.3.1.4 EEPROM Reset ...................................................................................18

3.3.1.5 Software Initiated Reset .......................................................................18

3.3.1.6 Hardware (HW) Standby or Suspend ..................................................18

3.3.1.7 Sof tware (SW) Suspend .....................................................................18

3.3.2 TAllowing Time for Reset Operation ....................................................................18

3.3.3 TBus Reset Considerations .................................................................................18

3.3.4 TInitialization ........................................................................................................19

3.4 Configurations with EEPROM ..........................................................................................20

3.4.1 TEEPROM Interface ............................................................................................20

3.4.2 TEEPROM Memory Organization ........................................................................20

3.4.3 TReset Configuration Block .................................................................................20

3.4.3.1 Reset Configuration Block Structure ....................................................20

3.4.3.2 Reset Configuration Block Header ......................................................20

3.4.3.3 Determining the EEPROM Type ..........................................................20

3.4.3.4 Checking EEPROM for presence of Reset Configuration Block ..........20

3.4.3.5 Determining Number of Bytes in the Reset Configuration Block .........21

3.4.4 TGroups of Configuration Data ............................................................................21

3.4.4.1 Group Header ......................................................................................22

3.4.5 TReset Configuration Block Checksum ...............................................................22

3.4.6 TEEPROM Example ............................................................................................22

3.4.7 TEEPROM Read-out ...........................................................................................22

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