MX828 查看數據表（PDF） - MX-COM Inc
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MX828 Datasheet PDF : 34 Pages
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CTCSS/DCS/SelCall Processor
13
MX828 PRELIMINARY INFORMATION
4.4.8 GENERAL PURPOSE TIMER (GPT) Register (Hex address $8B)
This register is used to preset the value of a countdown timer. Once a binary value has been loaded into this register, it
will be automatically transferred to an internal register within the timer. This internal register is then decremented at each
count interval (1ms) until it reaches zero. On reaching zero, the GPT IRQ FLAG in the IRQ FLAG Register (Hex address
$8F) is set to "1". An interrupt is generated on the IRQ pin if the GPT IRQ MASK in the IRQ MASK Register (Hex address
$8E) is "1" otherwise the GPT IRQ FLAG remains set to "1" and no interrupt is generated.
When the internal register has reached a count of zero, the action of the timer depends on the setting of the TIMER RE-
CYCLE bit in the GENERAL CONTROL Register (Hex address $88). If the TIMER RE-CYCLE bit is "1" then the timer will
re-load the countdown value from the GENERAL PURPOSE TIMER Register and restart the countdown from this value.
If the TIME RE-CYCLE bit is "0" then the timer will stop and no further action or timer interrupts will take place until the
GENERAL PURPOSE TIMER Register is re-loaded. Loading the GENERAL PURPOSE TIMER with "0" will cause the
timer circuitry to be disabled (i.e. powersaved).
4.4.9 IRQ MASK Register (Hex address $8E)
This register is used to control the interrupts (IRQs) as described below:
(Bits 7 and 1)
GPT IRQ MASK
(Bit 6)
COMP 0 to 1
IRQ MASK
(Bit 5)
COMP 0 to 1
IRQ MASK
(Bit 4)
TONE IRQ MASK
(Bit 3)
CTCSS FAST IRQ MASK
(Bit 2)
DCS IRQ MASK
(Bit 0)
Reserved for future use. These should be set to "0".
When this bit is set to "1" it enables an interrupt that occurs when GPT IRQ FLAG (Bit 6, IRQ
FLAG Register, $8F) changes from "0" to "1". When this bit is "0" the interrupt is masked.
When this bit is set to "1" it enables an interrupt that occurs when the comparator output
goes from "0" to "1". When this bit is set to "0" the interrupt is masked.
When this bit is set to "1" it enables an interrupt that occurs when the comparator output
goes from "1" to "0". When this bit is set to "0" the interrupt is masked.
When this bit is set to "1" it enables an interrupt that occurs when the TONE IRQ FLAG (Bit
3, IRQ FLAG Register, $8F) changes from "0" to "1". When this bit is "0" the interrupt is
masked.
When this bit is set to "1" it enables an interrupt that occurs when the CTCSS FAST IRQ
FLAG (Bit 2, IRQ FLAG Register, $8F) changes from "0" to "1". When this bit is "0" the
interrupt is masked.
When this bit is set to "1" it enables an interrupt that occurs when the DCS DECODE/NO
DECODE FLAG (Bit 7, SELCALL & SUB-AUDIO STATUS Register $81) changes state.
When this bit is set to "0" the interrupt is masked.
Table 12: IRQ MASK Register (Hex address $8E)
4.4.10 CTCSS TX/FAST RX FREQUENCY Register (Hex address $83)
This is a 16-bit register. Byte (1) is sent first. When the CTCSS fast detector is enabled, the bits 0 to 12 define the
receive frequency which the fast predictive detector is looking for according to the formula below:
A
=
fXTAL (Hz)
16 x fTONE (Hz)
where A is the binary number programmed into the 13 bits.
When the CTCSS transmitter is enabled, the bits 0 to 12 control the frequency of the transmitted CTCSS tones according
to the formula above.
When the fast detector and the transmitter are both enabled, bits 0-12 define the receive frequency which the fast
predictive detector is looking for and the frequency of the transmitted tone according to the formula above. (i.e. Tx Tone =
predictive tone).
When Bit 7 in byte (1) is set to "1" the tone output is set at VBIAS or NOTONE without regard to the number "A"
programmed. When Bit 7 is "0" the programmed tone is set on the output. Programming the bits 0 to 12 to "0" puts the Tx
into powersave and the output goes to VBIAS. Powersave is also achieved by disabling the SUBAUDIO Tx and the CTCSS
FAST DETECT.
© 1997 MX•COM Inc.
www.mxcom.com Tele: 800 638-5577 336 744-5050 Fax: 336 744-5054
Doc. # 20480161.002
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