MX828 查看數據表（PDF） - MX-COM Inc
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MX828 Datasheet PDF : 34 Pages
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CTCSS/DCS/SelCall Processor
17
MX828 PRELIMINARY INFORMATION
TONE DECODE
(Bit 4)
RX TONE
(Bits 3, 2, 1 and 0)
This bit indicates the status of the tone decoder. A "1" indicates a tone has been detected
(TONE DECODE) and a "0" indicates the loss of the tone (NOTONE).
TONE DECODE means that a tone has been decoded and its characteristics are defined by the
bandwidth (See SIGNALING SET-UP Register bits 7, 6, 5 and 4) and the RX TONE number
(See SELCALL and SUB-AUDIO STATUS Register bits 3, 2, 1 and 0).
When Bit 6 in the SIGNALING CONTROL Register is set to "0" the TONE DECODE bit 4 will be
set to "0".
Identification of a valid tone which is not in the pre-programmed list of up to 15 tones will cause
the decoder to move to the TONE DECODE state with the RX TONE address of "1111" in bits 3,
2, 1 and 0; indicating a valid, but unrecognized, tone. Loss of tone, will cause the NOTONE
timer to be started. If loss of tone continues for the duration of the timeout period, then the
decoder will move to NOTONE state and the identification of pre-programmed tones will start
again.
These four bits hold a Hex number from $0 to $F. Numbers $0 to $E represent the address of
the tone decoded according to the tones programmed in the RX TONE PROGRAM Register,
$84. The Hex number $F indicates the presence of any tone that is not described by
DECODER BANDWIDTH (Bits 7, 6, 5 and 4, SIGNALING SET-UP Register, $82) and
FREQUENCY (Bits 11 - 0, RX TONE PROGRAM Register, $84).
Table 16: SELCALL and SUB-AUDIO STATUS Register (Hex address $81)
4.6.2 IRQ FLAG Register (Hex address $8F)
This register is used to indicate when the device requires attention as below:
(Bits 7 and 1)
GPT IRQ FLAG
(Bit 6)
COMP 0 to 1
IRQ FLAG
(Bit 5)
COMP 1 to 0
IRQ FLAG
(Bit 4)
TONE IRQ FLAG
(Bit 3)
CTCSS FAST IRQ
FLAG
(Bit 2)
DCS IRQ FLAG
(Bit 0)
Reserved for future use. These will be set to "0" but should be ignored by user's software.
When the general purpose timer has reached zero in its internal register, this bit will be set to "1"
to indicate the timeout has expired. This bit is cleared to "0" by a read of the IRQ FLAG Register
(Hex address $8F).
When the comparator output goes from "0" to "1" (i.e. when the input voltage is above the DAC
output voltage) this bit will be set to "1" and an interrupt generated (if bit 5 of the IRQ MASK
Register $8E is set to "1"). This bit is set to "0" when the IRQ FLAG Register $8F is read.
When the comparator output goes from "1" to "0" this bit will be set to "1" and an interrupt
generated (if bit 4 of the IRQ MASK Register $8E is set to "1"). This bit is set to "0" when the IRQ
FLAG Register $8F is read.
When RX TONE DECODE (Bit 4, SELCALL and SUB-AUDIO STATUS Register, $81) changes
state this bit will be set to "1". This bit is cleared to "0" by a read of the IRQ FLAG Register (Hex
address $8F).
When CTCSS FAST TONE (Bit 6, SELCALL and SUB-AUDIO STATUS Register, $81) changes
state this bit will be set to "1". This bit is cleared to "0" by a read of the IRQ FLAG Register (Hex
address $8F).
When DCS DECODE/NO DECODE (Bit 7 SELCALL and SUB-AUDIO STATUS Register, $81)
changes state this bit will be set to "1". This bit is cleared to "0" by a read of the IRQ FLAG
Register (Hex address $8F).
Table 17: IRQ FLAG Register (Hex address $8F)
© 1997 MX•COM Inc.
www.mxcom.com Tele: 800 638-5577 336 744-5050 Fax: 336 744-5054
Doc. # 20480161.002
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