UCN-5801EP 查看數據表（PDF） - Allegro MicroSystems
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UCN-5801EP Datasheet PDF : 12 Pages
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5800 AND 5801
BiMOS II
LATCHED DRIVERS
SUPPLY
VDD
IN N
STROBE
FUNCTIONAL BLOCK DIAGRAM
COMMON
OUT N
CLEAR
OUTPUT ENABLE
COMMON MOS CONTROL
TYPICAL MOS LATCH
GROUND
TYPICAL BIPOLAR DRIVE
Dwg. FP-016-1
TYPICAL INPUT CIRCUIT
2.5
VDD
2.0
IN
1.5
22-PIN DIP, RθJA = 50°C/W
28-LEAD PLCC, R θJA = 55°C/W
14-PIN DIP, R θJA = 60°C/W
24-LEAD SOIC, R θJA = 68°C/W
Dwg. EP-010-4A
1.0
0.5
14-LEAD SOIC, R θJA = 95°C/W
0
25
50
75
100
125
150
AMBIENT TEMPERATURE IN °C
Dwg. GP-023-1
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
Copyright © 1985, 1997, Allegro MicroSystems, Inc.
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