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UMA1005

Dual low-power frequency synthesizer

Philips Electronics 

Philips Semiconductors

Dual low-power frequency synthesizer

Preliminary specification

UMA1005T

The loading of the work registers NM1, NM2, NM3, NM4

and PR is synchronized with the state of the main counter,

to avoid extra phase disturbance when switching over to

another main divider ratio as is explained in Section “Serial

programming input”.

At the completion of a main divider cycle, a main divider

output pulse is generated which will drive the main phase

comparator. Also the fractional accumulator is

incremented with NF. The accumulator works modulo Q.

Q is preset by the serial control bit FMOD to 8 when

FMOD = 1. Each time the accumulator overflows, the

feedback to the prescaler will select one cycle using

prescaler ratio R2 instead of R1.

As shown above, this will increase the overall division ratio

by 1 if R2 = R1 + 1. The mean division ratio over Q main

divider cycles will then be: NQ = N + N--Q---F--

Programming a fraction means the prescaler with main

divider will divide by N or N + 1.

The output of the main divider will be modulated with a

fractional phase ripple. This phase ripple is proportional to

the contents of the fractional accumulator FRD, which is

used for fractional current compensation.

Phase detectors (Fig.6)

The auxiliary and main phase detectors are a 2 D-type

flip-flop phase and frequency detector. The flip-flops are

set by the negative edges of output signals of the dividers.

The reset inputs are activated when both flip-flops have

been set and when the reset enable signal is active (LOW).

Around zero phase error this has the effect of delaying the

reset for 1 reference input cycle. This avoids non-linearity

or dead band around zero phase error. The flip-flops drive

on-chip charge pumps. A pull-up current from the charge

pump indicates that the VCO frequency shall be increased

while a pull-down pulse indicates that the VCO frequency

shall be decreased.

Current settings

The UMA1005T has 3 current setting pins RA, RN and RF.

The active charge pump currents and the fractional

compensation currents are linearly dependent on the

current in the current setting pins. This current IR can be

set by an external resistor to be connected between the

current setting pin (pin 9) and VSS. The typical value for R

(current setting resistor) can be calculated with the

equation:

R = --(--V----D----D----A----–-----0---.-I-5-R--)-----–----2----3---7--------I--R--

The current can be set to zero by connecting the

corresponding pin to VDDA.

Auxiliary output charge pumps

The auxiliary charge pumps on pin PHA are driven by the

auxiliary phase detector and the current value is

determined by the external resistor (Rext) at pin RA. The

active charge pump current is typically: |IPHA| = 8 × IRA.

Main output charge pumps and fractional

compensation currents

The main charge pumps on pins PHP and PHI are driven

by the main phase detector and the current value is

determined by the current at pin RN and via a number of

DACs which are driven by registers of the serial input. The

fractional compensation current is determined by the

current at pin RF, the contents of the fractional

accumulator FRD and a number of DACs driven by

registers from the serial input. The timing for the fractional

compensation is derived from the reference divider. The

current is on during 1 input reference cycle before and

1 cycle after the output signal to the phase comparator.

Figure 7 shows the waveforms for a typical case.

When the serial input A word is loaded, the output circuits

are in the ‘speed-up mode’ as long as the STROBE is

HIGH, else the ‘normal mode’ is active.

NORMAL MODE

In the ‘normal mode’ the current output at PHP is:

IPHP(N) = Ipump10 + Icomp10.

Where:

Ipump10 = -C----N----2--×--9---I--R---N-- ; charge pump current.

Icomp10 = F-----R----1D----2--×-8----I--R----F- ; fractional compensation current.

In ‘normal mode’ the current at output PHI is zero.

November 1994

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