UPA1721G-E2 查看數據表（PDF） - NEC => Renesas Technology
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UPA1721G-E2 Datasheet PDF : 8 Pages
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µ PA1721
ELECTRICAL CHARACTERISTICS (TA = 25 °C, All terminals are connected.)
CHARACTERISTICS
SYMBOL
TEST CONDITIONS
MIN. TYP. MAX. UNIT
Drain to Source On-state Resistance
RDS(on)1
RDS(on)2
RDS(on)3
VGS = 10 V, ID = 5.0 A
VGS = 4.5 V, ID = 5.0 A
VGS = 4.0 V, ID = 5.0 A
8.0 10.5 mΩ
10.0 14.0 mΩ
12.0 17.0 mΩ
Gate to Source Cut-off Voltage
VGS(off) VDS = 10 V, ID = 1 mA
1.5 2.0 2.5 V
Forward Transfer Admittance
Drain Leakage Current
Gate to Source Leakage Current
| yfs |
IDSS
IGSS
VDS = 10 V, ID = 5.0 A
VDS = 30 V, VGS = 0 V
VGS = ±20 V, VDS = 0 V
7.0 14.0
S
10 µA
±10 µA
Input Capacitance
Ciss
VDS = 10 V
2200
pF
Output Capacitance
Coss
VGS = 0 V
710
pF
Reverse Transfer Capacitance
Crss
f = 1 MHz
270
pF
Turn-on Delay Time
td(on)
ID = 5.0 A
30
ns
Rise Time
tr
VGS(on) = 10 V
90
ns
Turn-off Delay Time
Fall Time
td(off)
tf
VDD = 15 V
RG = 10 Ω
90
ns
50
ns
Total Gate Charge
QG
ID = 10 A
39
nC
Gate to Source Charge
QGS
VDD = 24 V
6.3
nC
Gate to Drain Charge
QGD
VGS = 10 V
10.0
nC
Body Diode Forward Voltage
VF(S-D) IF = 10 A, VGS = 0 V
0.8
V
Reverse Recovery Time
Reverse Recovery Charge
trr
IF = 10 A, VGS = 0 V
Qrr
di/dt = 100 A/ µs
40
ns
50
nC
TEST CIRCUIT 1 SWITCHING TIME
D.U.T.
RG
PG.
RG = 10 Ω
VGS
0
τ
τ = 1µ s
Duty Cycle ≤ 1 %
RL
VDD
VGS
VGS
Wave Form
10 %
0
VGS(on)
ID
90 %
ID
Wave Form
0 10 %
td(on)
ID
tr
td(off)
90 %
90 %
10 %
tf
ton
toff
TEST CIRCUIT 2 GATE CHARGE
D.U.T.
IG = 2 mA
RL
PG.
50 Ω
VDD
2
Data Sheet G13889EJ1V0DS00
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