UPA1724 查看數據表（PDF） - NEC => Renesas Technology
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UPA1724 Datasheet PDF : 8 Pages
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µ PA1724
ELECTRICAL CHARACTERISTICS (TA = 25 °C, All terminals are connected.)
CHARACTERISTICS
SYMBOL
TEST CONDITIONS
MIN. TYP. MAX. UNIT
Drain to Source On-state Resistance
5
Gate to Source Cut-off Voltage
Forward Transfer Admittance
Drain Leakage Current
Gate to Source Leakage Current
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Turn-on Delay Time
Rise Time
Turn-off Delay Time
Fall Time
Total Gate Charge
5 Gate to Source Charge
5 Gate to Drain Charge
RDS(on)1
RDS(on)2
RDS(on)3
VGS(off)
| yfs |
IDSS
IGSS
Ciss
Coss
Crss
td(on)
tr
td(off)
tf
QG
QGS
QGD
VGS = 4.5 V, ID = 5.0 A
VGS = 4.0 V, ID = 5.0 A
VGS = 2.5 V, ID = 5.0 A
VDS = 10 V, ID = 1 mA
VDS = 10 V, ID = 5.0 A
VDS = 20 V, VGS = 0 V
VGS = ±12 V, VDS = 0 V
VDS = 10 V
VGS = 0 V
f = 1 MHz
ID = 5.0 A
VGS(on) = 4.5 V
VDD = 10 V
RG = 10 Ω
ID = 10 A
VDD = 16 V
VGS = 4.5 V
8.6 11.0 mΩ
8.8 12.0 mΩ
11.0 15.0 mΩ
0.5 0.84 1.5 V
10.0 19
S
10 µA
±10 µA
1850
pF
610
pF
320
pF
43
ns
170
ns
90
ns
130
ns
18
nC
3.2
nC
7.8
nC
Body Diode Forward Voltage
Reverse Recovery Time
VF(S-D)
trr
IF = 10 A, VGS = 0 V
IF = 10 A, VGS = 0 V
0.78
V
45
ns
Reverse Recovery Charge
Qrr
di/dt = 100 A / µs
40
nC
TEST CIRCUIT 1 SWITCHING TIME
D.U.T.
RG
PG.
RG = 10 Ω
VGS
0
τ
τ = 1µ s
Duty Cycle ≤ 1 %
RL
VDD
VGS
VGS
Wave Form
010 %
VGS(on)
ID
90 %
ID
Wave Form
0 10 %
td(on)
ID
tr
td(off)
90 %
90 %
10 %
tf
ton
toff
TEST CIRCUIT 2 GATE CHARGE
D.U.T.
IG = 2 mA
RL
PG.
50 Ω
VDD
2
Data Sheet G14048EJ1V0DS00
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