UPA1750 查看數據表（PDF） - NEC => Renesas Technology
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UPA1750 Datasheet PDF : 8 Pages
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µPA1750
ELECTRICAL CHARACTERISTICS (TA = 25 ˚C, all terminals are connected.)
Characteristics
Drain to Source On-state Resistance
Gate to Source Cutoff Voltage
Forward Transfer Admittance
Drain Leakage Current
Gate to Source Leakage Current
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Turn-On Delay Time
Rise Time
Turn-off Delay Time
Fall Time
Total Gate Charge
Gate to Source Charge
Gate to Drain Charge
Body Diode Forward Voltage
Reverse Recovery Time
Reverse Recovery Charge
Symbol
RDS(on)1
RDS(on)2
VGS(off)
| yfs |
IDSS
IGSS
Ciss
Coss
Crss
td(on)
tr
td(off)
tf
QG
QGS
QGD
VF(S-D)
trr
Qrr
Test Conditions
VGS = –10 V, ID = –1.8 A
VGS = –4 V, ID = –1.8 A
VDS = –10 V, ID = –1 mA
VDS = –10 V, ID = –1.8 A
VDS = –20 V, VGS = 0
VGS = 20 V, VDS = 0
VDS = –10 V
VGS = 0
f = 1 MHz
ID = –1.8 A
VGS(on) = –10 V
VDD = –10 V
RG = 10 Ω
ID = –3.5 A
VDD = –16 V
VGS = –10 V
IF = 3.5 A, VGS = 0
IF = 3.5 A, VGS = 0
di/dt = 100 A/µs
Min. Typ. Max. Unit
0.065 0.090
Ω
0.125 0.180
Ω
–1.0 –1.7 –2.5
V
2.0
4.4
S
–10
µA
10
µA
540
pF
385
pF
105
pF
10
ns
110
ns
340
ns
230
ns
18
nC
2.0
nC
5.1
nC
0.8
V
160
ns
310
nC
Test Circuit 1 Switching Time
D.U.T.
RG
PG. RG = 10 Ω
VGS
0
t
t = 1 µs
Duty Cycle ≤ 1 %
RL
VDD
VGS
VGS
Wave Form
10 %
0
VGS(on)
ID
90 %
ID
ID
0 10 %
Wave Form
90 %
90 %
10 %
td(on)
tr
td(off)
tf
ton
toff
Test Circuit 2 Gate Charge
D.U.T.
IG = 2 mA
RL
PG.
50 Ω
VDD
2
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