UPA1759 查看數據表（PDF） - NEC => Renesas Technology
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UPA1759 Datasheet PDF : 4 Pages
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µPA1759
ELECTRICAL CHARACTERISTICS (TA = 25 °C, All terminals are connected.)
CHARACTERISTICS
SYMBOL
TEST CONDITIONS
MIN.
Drain to Source On-state Resistance
RDS(on)1 VGS = 10 V, ID = 2.5 A
RDS(on)2 VGS = 4 V, ID = 2.5 A
Gate to Source Cut-off Voltage
VGS(off) VDS = 10 V, ID = 1 mA
1.0
Forward Transfer Admittance
| yfs | VDS = 10 V, ID = 2.5 A
2.0
Drain Leakage Current
IDSS
VDS = 60 V, VGS = 0 V
Gate to Source Leakage Current
IGSS
VGS = ±20 V, VDS = 0 V
Input Capacitance
Ciss
VDS = 10 V
Output Capacitance
Coss
VGS = 0 V
Reverse Transfer Capacitance
Crss
f = 1 MHz
Turn-on Delay Time
td(on)
ID = 2.5 A
Rise Time
tr
VGS(on) = 10 V
Turn-off Delay Time
td(off)
VDD = 15 V
Fall Time
tf
RG = 10 Ω
Total Gate Charge
QG
ID = 5.0 A
Gate to Source Charge
QGS
VDD = 24 V
Gate to Drain Charge
QGD
VGS = 10 V
Body Diode forward Voltage
VF(S-D) IF = 5.0 A, VGS = 0 V
Reverse Recovery Time
trr
IF = 5.0 A, VGS = 0 V
Reverse Recovery Charge
Qrr
di/dt = 100 A/µs
TYP.
110
170
1.7
3.9
190
100
36
6
50
80
50
8
1
2.4
0.9
40
50
MAX. UNIT
150 mΩ
240 mΩ
2.5
V
S
10
µA
±10 µA
pF
pF
pF
ns
ns
ns
ns
nC
nC
nC
V
ns
nC
TEST CIRCUIT 1 AVALANCHE CAPABILITY
TEST CIRCUIT 2 SWITCHING TIME
D.U.T.
RG = 25 Ω
L
PG.
50 Ω
VDD
VGS = 20 → 0 V
IAS
ID
VDD
BVDSS
VDS
Starting Tch
TEST CIRCUIT 3 GATE CHARGE
D.U.T.
PG.
RG
RG = 10 Ω
VGS
0
τ
τ = 1 µs
Duty Cycle ≤ 1 %
RL
VDD
VGS
VGS
Wave Form
10 %
0
ID
ID
Wave Form
0 10 %
VGS(on) 90 %
90 %
ID
90 %
10 %
td(on)
tr td(off)
tf
ton
toff
D.U.T.
IG = 2 mA
RL
PG.
50 Ω
VDD
2
Data Sheet G13622EJ1V0DS00
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