UPA1792 查看數據表（PDF） - NEC => Renesas Technology

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UPA1792

SWITCHING N- AND P-CHANNEL POWER MOS FET INDUSTRIAL USE

NEC => Renesas Technology 

µPA1792

ELECTRICAL CHARACTERISTICS (TA = 25°C, All terminals are connected.)

N-CHANNEL

CHARACTERISTICS

SYMBOL

TEST CONDITIONS

MIN. TYP. MAX. UNIT

Drain to Source On-state Resistance

Gate to Source Cut-off Voltage

Forward Transfer Admittance

Drain Leakage Current

Gate to Source Leakage Current

RDS(on)1

RDS(on)2

RDS(on)3

VGS(off)

| yfs |

IDSS

IGSS

VGS = 10 V, ID = 3.4 A

VGS = 4.5 V, ID = 3.4 A

VGS = 4.0 V, ID = 3.4 A

VDS = 10 V, ID = 1 mA

VDS = 10 V, ID =3.4 A

VDS = 30 V, VGS = 0 V

VGS = ±16 V, VDS = 0 V

20.5 26 mΩ

27 36 mΩ

31 42 mΩ

1.5 2.1 2.5 V

3.0 7.5

S

10 µA

±10 µA

Input Capacitance

Ciss

VDS = 10 V

760

pF

Output Capacitance

Coss

VGS = 0 V

250

pF

Reverse Transfer Capacitance

Turn-on Delay Time

Crss

td(on)

f = 1 MHz

ID = 3.4 A

95

pF

20

ns

Rise Time

tr

VGS(on) = 10 V

140

ns

Turn-off Delay Time

Fall Time

Total Gate Charge

Gate to Source Charge

td(off)

tf

QG

QGS

VDD = 15 V

RG = 10 Ω

ID = 6.8 A

VDD = 24 V

50

ns

30

ns

14

nC

2

nC

Gate to Drain Charge

QGD

VGS = 10 V

5

nC

Body Diode Forward Voltage

VF(S-D) IF = 6.8 A, VGS = 0 V

0.86

V

Reverse Recovery Time

trr

IF = 6.8 A, VGS = 0 V

30

ns

Reverse Recovery Charge

Qrr

di/dt = 100 A / µs

20

nC

TEST CIRCUIT 1 SWITCHING TIME

D.U.T.

RG

PG.

VGS

0

τ

τ = 1µs

Duty Cycle ≤ 1 %

RL

VGS

VGS

Wave Form

10 %

0

VGS(on) 90 %

VDD

ID

90 %

ID

ID

0 10 %

Wave Form

90 %

10 %

td(on) tr td(off) tf

ton

toff

TEST CIRCUIT 2 GATE CHARGE

D.U.T.

IG = 2 mA

RL

PG.

50 Ω

VDD

Data Sheet G14557EJ1V0DS00

3

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