UPA1792 查看數據表（PDF） - NEC => Renesas Technology

零件编号

产品描述 (功能)

生产厂家

UPA1792

SWITCHING N- AND P-CHANNEL POWER MOS FET INDUSTRIAL USE

NEC => Renesas Technology 

P-CHANNEL

CHARACTERISTICS

Drain to Source On-state Resistance

Gate to Source Cut-off Voltage

Forward Transfer Admittance

Drain Leakage Current

Gate to Source Leakage Current

Input Capacitance

Output Capacitance

Reverse Transfer Capacitance

Turn-on Delay Time

Rise Time

Turn-off Delay Time

Fall Time

Total Gate Charge

Gate to Source Charge

Gate to Drain Charge

Body Diode Forward Voltage

Reverse Recovery Time

Reverse Recovery Charge

SYMBOL

TEST CONDITIONS

RDS(on)1

RDS(on)2

RDS(on)3

VGS(off)

| yfs |

IDSS

IGSS

Ciss

Coss

Crss

td(on)

tr

td(off)

tf

QG

QGS

QGD

VF(S-D)

VGS = –10 V, ID = –2.9 A

VGS = –4.5 V, ID = –2.9 A

VGS = –4.0 V, ID = –2.9 A

VDS = –10 V, ID = –1 mA

VDS = –10 V, ID = –2.9 A

VDS = –30 V, VGS = 0 V

VGS = # 16 V, VDS = 0 V

VDS = –10 V

VGS = 0 V

f = 1 MHz

ID = –2.9 A

VGS(on) = –10 V

VDD = –15 V

RG = 10 Ω

ID = –5.8 A

VDD = –24 V

VGS = –10 V

IF = 5.8 A, VGS = 0 V

trr

IF = 5.8 A, VGS = 0 V

Qrr

di/dt = 100 A / µs

µPA1792

MIN. TYP. MAX. UNIT

30 36 mΩ

43 54 mΩ

49 65 mΩ

–1.5 –2.0 –2.5 V

3.5 8.0

S

–1 µA

# 10 µA

900

pF

300

pF

120

pF

23

ns

220

ns

90

ns

70

ns

17

nC

2.5

nC

4.0

nC

0.85

V

40

ns

30

nC

TEST CIRCUIT 1 SWITCHING TIME

D.U.T.

RG

PG.

VGS (−)

0

τ

τ = 1µs

Duty Cycle ≤ 1 %

RL

VGS (−)

VGS

Wave Form

010 %

VGS(on) 90 %

VDD

ID (−)

90 %

ID

ID

0 10 %

Wave Form

90 %

10 %

td(on) tr td(off) tf

ton

toff

TEST CIRCUIT 2 GATE CHARGE

D.U.T.

IG = −2 mA

RL

PG.

50 Ω

VDD

4

Data Sheet G14557EJ1V0DS00

Share Link: