UPB1502GR-E2 查看數據表（PDF） - NEC => Renesas Technology

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UPB1502GR-E2

1.7 GHz/ 2.0 GHz LOW-POWER TWO-MODULUS PRESCALER DIVIDED-BY-64/65, 128/129

NEC => Renesas Technology 

TIMING DIAGRAM

Divided by 64/65 SW ’H’

(Divided by 128/129 SW ’L’)

64 clocks

(128)

IN

µPB1502GR, 1502GR(1)

65 clocks

(129)

OUT

32 clocks

(64)

32 clocks

(64)

32 32 32 32 32 32

(64) (64) (64) (64) (64) (64)

32 clocks

(64)

33 clocks

(65)

32

32

33 32

33

33

(64) (64) (65) (64) (65) (65)

Hi

tset

M

LO

tset = The minimum time required between ‘Modulus Control’ going low and next output rising edge, in order to ensure a P+1

modulus change.

6

Data Sheet P10871EJ3V0DS00

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