UPB1003GS 查看數據表（PDF） - NEC => Renesas Technology
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UPB1003GS Datasheet PDF : 20 Pages
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µPB1005GS
ELECTRICAL CHARACTERISTICS (Unless otherwise specified, TA = +25°C, VCC = 3.0 V)
Parameter
Symbol
Conditions
MIN.
TYP.
Total Circuit Current
ICCtotal
ICC1 + ICC2 + ICC3 + ICC4
32.0
45.0
RF Down-converter Block (fRFin = 1575.42 MHz, f1stLOin = 1636.80 MHz, PLOin = −10 dBm, ZL = ZS = 50 Ω)
Circuit Current 1
ICC1
No Signals
6.0
10.0
RF Conversion Gain
RF-SSB Noise Figure
CGRF
NFRF
PRFin = −40 dBm
PRFin = −40 dBm
12.5
15.5
7
10
Maximum IF Output Power
PO(sat)RF
PRFin = −10 dBm
−5.5
−2.5
IF Down-converter Block (f1stIFIn = 61.38 MHz, f2ndLOIn = 65.472 MHz, ZS = 50 Ω, ZL = 2 kΩ)
Circuit Current 2
ICC2
No Signals
3.4
5.3
IF Voltage Conversion Gain
CG(GV)IF at Maximum Gain, P1stIFin = −50 dBm
38
41
IF-SSB Noise Figure
NFIF
at Maximum Gain, P1stIFin = −50 dBm
8.5
11.5
Maximum 2nd IF Output
Power
PO(sat)IF
at Maximum Gain, P1stIFin = −20 dBm
−9.5
−6.5
Gain Control Voltage
VGC
Voltage at Maximum Gain of CGIF
Gain Control Range
DGC
P1stIFin = −50 dBm
2nd IF Amplifier (f2ndIF = 4.092 MHz, ZS = 50 Ω, ZL = 2 kΩ)
20
Circuit Current 3
ICC3
No Signals
1.55
2.40
Voltage Gain
GV
P2ndIFin = −60 dBm
37
40
Maximum Output Power
PO(sat)
P2ndIFin = −30 dBm
−14.5 −11.5
PLL Synthesizer Block
Circuit Current 4
ICC4
PLL All Block Operating
18.5
28.5
Phase Comparing
Frequency
fPD
PLL Loop
8.0
8.184
Reference Input Minimum
Level
VREFin
ZL = 10 kΩ//20 pF (Impedance of
measurement equipment)
200
Loop Filter Output Level (H)
VLP(H)
2.8
Loop Filter Output Level (L)
VLP(L)
Reference Output Swing
VREFout
ZL = 10 kΩ//2 pF (Impedance of
measurement equipment)
1.0
MAX.
60.0
14.0
18.5
13
+0.5
7.2
44
14.5
−3.5
1.0
3.25
43
−8.5
38.5
8.4
0.4
Unit
mA
mA
dB
dB
dBm
mA
dB
dB
dBm
V
dB
mA
dB
dBm
mA
MHz
mVP-P
V
V
VP-P
Data Sheet P13860EJ3V0DS00
5
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