UPD16654 查看數據表（PDF） - NEC => Renesas Technology
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UPD16654 Datasheet PDF : 16 Pages
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µPD16654
Switching Characteristics (TA = –20 to +70°C, VDD1 = 25 V, VDD2 = 3.3 V ± 0.3 V, VEE1 = VEE2 = –15 V, VSS = 0 V)
Parameter
Cascade output delay time
Driver output delay time 1
Driver output delay time 2
Output rise time
Output fall time
Input capacitance
Maximum clock frequency
Symbol
tPHL1
tPLH1
tPHL2
tPLH2
tPHL3
tPLH3
tTLH
tTHL
CI
fmax.
Condition
CL = 20 pF
CLK → STVL (STVR)
CL = 300 pF
CLK → On
CL = 300 pF
OEn → On
CL = 300 pF
TA = 25°C
When connected in cascade
MIN.
500
TYP.
MAX.
Unit
800
ns
800
ns
500
ns
500
ns
500
ns
500
ns
450
ns
450
ns
15
pF
kHz
Timing Requirement (TA = –20 to +70°C, VDD1 = 25 V, VDD2 = 3.3 V ± 0.3 V, VEE1 = VEE2 = –15 V, VSS = 0 V)
Parameter
Clock Pulse Low Period
Clock Pulse High Period
Enable Pulse low period
Data Setup Time
Data Hold Time
Symbol
PWCLK(H)
PWCLK(L)
PWOE
tSETUP
tHOLD
Condition
STVR (STVL) ↑ → CLK ↑
CLK ↑ → STVR (STVL) ↓
MIN.
500
500
1.0
200
200
TYP.
MAX.
Unit
ns
ns
µs
ns
ns
The rise and fall times of logic input must be tr = tf = 20 ns (10% to 90%).
10
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